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GS8160V18AT-150 Datasheet(PDF) 7 Page - GSI Technology |
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GS8160V18AT-150 Datasheet(HTML) 7 Page - GSI Technology |
7 / 24 page Rev: 1.00a 6/2003 7/24 © 2003, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160V18/32/36AT-350/333/300/250/200/150 Preliminary Note: There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences BPR 1999.05.18 Mode Pin Functions Mode Name Pin Name State Function Burst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, IDD = ISB Linear Burst Sequence Note: The burst counter wraps to initial state on the 5th clock. Interleaved Burst Sequence Note: The burst counter wraps to initial state on the 5th clock. A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 |
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