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GS880F36BT-5 Datasheet(PDF) 7 Page - GSI Technology |
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GS880F36BT-5 Datasheet(HTML) 7 Page - GSI Technology |
7 / 27 page GS880F18/32/36BT-4.5/5/5.5/6.5/7.5 Rev: 1.02 10/2004 7/27 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Note: There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences BPR 1999.05.18 Mode Pin Functions Mode Name Pin Name State Function Burst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, IDD = ISB Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 |
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