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IR2177S Datasheet(PDF) 11 Page - International Rectifier |
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IR2177S Datasheet(HTML) 11 Page - International Rectifier |
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11 / 20 page  IR2277S/IR2177S(PbF) 11 www.irf.com 1 Device Description 1.1 SYNC input Sync input clocks the whole device. In order to make the device work properly it must be synchronous with the triangular PWM carrier as shown in Figure 8. SYNC pin is internally pulled-down (10 k Ω) to V SS. 1.2 PWM Output (PO) PWM output is an open collector output (active low). It must be pulled-up to proper supply with an external resistor (suggested value between 500 Ω and 10k Ω). Figure 7: PO rising and falling slopes PO pull-up resistor determines the rising slope of the PO output and the lower value of PO as shown in Figure 7, where RC = τ , C is the total PO pin capacitance and R is the pull-up resistance. up pull on on low R R R Supply V − + ⋅ = where Ron is the internal open collector resistance and Rpull-up is the external pull-up resistance. PO duty cycle is defined for active low logic by the following formula: Eq. 1 n cycle n cycle off n T T D _ 1 _ _ + = PO duty cycle ( Dn) swings between 10% and 30%. Zero input voltage corresponds to 20% duty cycle. A residual offset can be read in PO duty cycle according to VPOs (see Static electrical characteristics). According to Figure 8, it can be assumed that odd cycles are represented by SYNC at high level (let’s name channel 1 the output related to this state of SYNC) and even cycles represented by SYNC at low level (channel 2). The two channels are independent in order to provide the correct duty cycle value of PO even for non-50% duty cycle of SYNC signal. Small variation of SYNC duty cycle are then allowed and automatically corrected when calculating the duty cycle using Eq. 1. However, channel 1 and channel 2 can have a difference in offset value which is specified in ∆V POS (see Static electrical characteristics). To implement a correct offset compensation of PO duty cycle and analog OUT, each channel must be compensated separately. 1.3 Over Current output (OC) OC output is an open drain pin (active low). A simplified block diagram of the over current circuit is shown in the Figure 9. Over current is detected when | Vin|=|Vinp-Vinm|>VOCth. If an event of over current lasts longer than tdOCon, OC pin is forced to VSS and remains latched until PO is externally forced low for at least tOCoff (see timing on Figure 4). During an over current event (OC is low), PO is off (pulled-up by external resistor). If OC is reset by PO and over current is still active, OC pin will be forced low again by the next edge of SYNC signal. To reset OC state PO must be forced to VSS for at least TOCoff. • Autoreset function The autoreset function consists in clearing automatically the OC fault. To enable the autoreset function, simply short circuit the OC pin with the PO pin. τ Vlow Supply |
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