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74ABT16260DL Datasheet(PDF) 6 Page - NXP Semiconductors |
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74ABT16260DL Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 12 page Philips Semiconductors Product specification 74ABT16260 74ABTH16260 12-bit to 24-bit multiplexed D-type latches (3-State) 1998 Feb 10 6 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = –40°C to +85 °C UNIT Min Typ Max Min Max VIK Input clamp voltage VCC = 4.5V; IIK = –18mA –0.8 –1.2 –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VOH High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V II Input leakage current VCC = 5.5V; VI = VCC or GND Control pins ±0.01 ±1 ±1 µA I g VCC = 5.5V; VI = VCC or GND Data pins ±3 ±5 µA VCC = 4.5V; VI = 0.8V A or B 75 75 IHOLD Bus Hold current VCC = 4.5V; VI = 2.0V ports –75 –75 µA VCC = 5.5V; VI = 0 to 5.5V ±500 ±500 IOFF Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA IPU/IPD Power-up/down 3-State output current VCC = 2.0V; VO = 0.5V; VI = GND or VCC; VOE = VCC ±60 ±200 ±200 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 1.0 10 10 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –1.0 –10 –10 µA ICEX Output high leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 50 50 µA IO Output current1 VCC = 5.5V; VO = 2.5V –50 –100 –225 –50 –225 mA VCC = 5.5V; Outputs High, VI = GND or VCC 0.2 1.5 1.5 ICC Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or VCC 8 19 19 mA ICC Quiescent su ly current VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.1 1.0 1.0 mA ∆ICC Additional supply current per input pin2 Outputs enabled, one input at 3.4V, other inputs at VCC or GND; VCC = 5.5V 0.1 1.5 1.5 mA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 3. This is the bus hold minimum overdrive current required to force the input to the opposite logic state. |
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