XRT75R03IV datasheet(4/92 Pages) EXAR

Part #	XRT75R03IV

Description	THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

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XRT75R03

xr

REV. 1.0.7

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

I

GENERAL DESCRIPTION .................................................................................................1

FEATURES .........................................................................................................................1

APPLICATIONS................................................................................................................................................1

FIGURE 1. BLOCK DIAGRAM OF THE XRT 75R03.............................................................................................................................. 2

TRANSMIT INTERFACE CHARACTERISTICS ........................................................................................................2

RECEIVE INTERFACE CHARACTERISTICS..........................................................................................................2

FIGURE 2. PIN OUT OF THE XRT75R03 ........................................................................................................................................... 3

ORDERING INFORMATION.....................................................................................................................3

PIN DESCRIPTIONS (BY FUNCTION) ..............................................................................4

SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS .......................................................................4

TRANSMIT LINE SIDE PINS..............................................................................................................................8

SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS ......................................................................10

RECEIVE LINE SIDE PINS ..............................................................................................................................17

GENERAL CONTROL PINS .............................................................................................................................18

CONTROL AND ALARM INTERFACE.................................................................................................................20

JITTER ATTENUATOR INTERFACE...................................................................................................................20

POWER SUPPLY AND GROUND PINS .............................................................................................................22

XRT75R03 PIN LISTING IN NUMERICAL ORDER ............................................................................................24

1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY) ........................................29

1.1 NETWORK ARCHITECTURE ......................................................................................................................... 29

FIGURE 3. NETWORK REDUNDANCY ARCHITECTURE ...................................................................................................................... 29

1.2 POWER FAILURE PROTECTION .................................................................................................................. 29

1.3 SOFTWARE VS HARDWARE AUTOMATIC PROTECTION SWITCHING ................................................... 29

2.0 ELECTRICAL CHARACTERISTICS ....................................................................................................30

TABLE 1: ABSOLUTE MAXIMUM RATINGS......................................................................................................................................... 30

TABLE 2: DC ELECTRICAL CHARACTERISTICS: ................................................................................................................................ 30

3.0 TIMING CHARACTERISTICS ..............................................................................................................31

FIGURE 4. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75R03 (DUAL-RAIL DATA) .......................................... 31

FIGURE 5. TRANSMITTER TERMINAL INPUT TIMING .......................................................................................................................... 31

FIGURE 6. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING ................................................................................................... 32

FIGURE 7. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES................................................................. 32

4.0 LINE SIDE CHARACTERISTICS: ........................................................................................................33

4.1 E3 LINE SIDE PARAMETERS: ...................................................................................................................... 33

FIGURE 8. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703 ......................................................................... 33

TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS........................................................ 34

FIGURE 9. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS............................. 35

TABLE 4: STS-1 PULSE MASK EQUATIONS ..................................................................................................................................... 35

TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) .............................. 36

FIGURE 10. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ................................................................... 37

TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................................................ 37

TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ................................. 38

FIGURE 11. MICROPROCESSOR SERIAL INTERFACE STRUCTURE...................................................................................................... 38

FIGURE 12. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ................................................................................ 39

TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) .................................. 39

FUNCTIONAL DESCRIPTION: ........................................................................................40

5.0 THE TRANSMITTER SECTION: ..........................................................................................................40

FIGURE 13. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED) ............................................................ 40

FIGURE 14. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED) ............................................................................. 40

5.1 TRANSMIT CLOCK: ....................................................................................................................................... 41

5.2 B3ZS/HDB3 ENCODER: ................................................................................................................................. 41

5.2.1 B3ZS ENCODING: ...................................................................................................................................................... 41

FIGURE 15. B3ZS ENCODING FORMAT ........................................................................................................................................... 41

5.2.2 HDB3 ENCODING:...................................................................................................................................................... 41

FIGURE 16. HDB3 ENCODING FORMAT .......................................................................................................................................... 41

5.3 TRANSMIT PULSE SHAPER: ........................................................................................................................ 42

5.3.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT: ................................................................................. 42

5.3.2 INTERFACING TO THE LINE: .................................................................................................................................... 42

5.4 TRANSMIT DRIVE MONITOR: ....................................................................................................................... 43

FIGURE 17. TRANSMIT DRIVER MONITOR SET-UP. ........................................................................................................................... 43

5.5 TRANSMITTER SECTION ON/OFF: .............................................................................................................. 43

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