Electronic Components Datasheet Search |
|
XR19L200IL32 Datasheet(PDF) 7 Page - Exar Corporation |
|
XR19L200IL32 Datasheet(HTML) 7 Page - Exar Corporation |
7 / 40 page PRELIMINARY XR19L200 7 REV. P1.0.2 SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER 2.2 5-Volt Tolerant Inputs The CMOS/TTL level inputs of the L200 can accept up to 5V inputs when operating at 3.3V. Note that the XTAL1 pin is not 5V tolerant when an external clock supply is used. 2.3 Device Hardware Reset The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 11). An active pulse of longer than 40 ns duration will be required to activate the reset function in the device. 2.4 Device Identification and Revision The XR19L200 provides a Device Identification code and a Device Revision code to distinguish the part from other devices and revisions. To read the identification code from the part, it is required to set the baud rate generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x01 to indicate functional compatibility with XR16L580 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means revision A. 2.5 Internal Registers The L200 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers, (LSR/LCR), modem status and control registers (MSR/ MCR), programmable data rate (clock) divisor registers (DLL/DLM), and an user accessible Scratchpad register (SPR). Beyond the general 16C550 features and capabilities, the L200 offers enhanced feature registers just like the XR16L580, namely, EFR, Xon1, Xoff 1, Xon1 and Xoff2 that provide automatic Xon/Xoff software flow control. All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 15. 2.6 DMA Mode The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the XR19L200. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’. 2.7 INT (IRQ#) Output The interrupt output changes according to the operating mode and enhanced features setup. Table 1 and Table 2 below summarize the operating behavior for the transmitter and receiver in the Intel and Motorola modes. Also see Figures 16 through 19. TABLE 1: INT (IRQ#) PIN OPERATION FOR TRANSMITTER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) INT Pin (I/M# = 1) 0 = one byte in THR 1 = THR empty 0 = FIFO above trigger level 1 = FIFO below trigger level or FIFO empty IRQ# Pin (I/M# = 0) 1 = one byte in THR 0 = THR empty 1 = FIFO above trigger level 0 = FIFO below trigger level or FIFO empty |
Similar Part No. - XR19L200IL32 |
|
Similar Description - XR19L200IL32 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |