XR19L200

PRELIMINARY

6

SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

REV. P1.0.2

2.0

FUNCTIONAL DESCRIPTIONS

2.1

CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The L200 data interface supports the Intel compatible types of CPUs and it is compatible to

the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus

transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus

interconnection for Intel and Motorola mode is shown in Figure 3.

VCC

VCC

A0

A1

A2

UART_CS#

IOR#

IOW#

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

CS#

D0

D1

D2

D3

D4

D5

D6

D7

IOR#

IOW#

UART_INT

INT

RS-232

Interface

Intel Data Bus Interconnections

GND

UART_RESET

RESET

16/68#

RX

TX

ACP

ACP

VCC

VCC

A0

A1

A2

UART_CS#

R/W#

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

CS#

D0

D1

D2

D3

D4

D5

D6

D7

IOR#

IOW#

UART_IRQ#

INT

Motorola Data Bus Interconnections

GND

UART_RESET#

RESET

RX

TX

ACP

VCC

16/68#

RS-232

Interface

ACP

4.7K

VCC