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XR17V252 Datasheet(PDF) 27 Page - Exar Corporation |
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XR17V252 Datasheet(HTML) 27 Page - Exar Corporation |
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27 / 69 page  XR17V252 27 REV. 1.0.1 66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT 3.1.3 Tx FIFO Data Loading at locations 0x100 (channel 0) and 0x300 (channel 1) The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation (maximum 16 DWORD writes) at memory locations 0x100 (channel 0) and 0x300 (channel 1). 3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8-BIT FORMAT The THR and RHR register address for channel 0 to channel 1 is shown in Table 11 below. The THR and RHR for each channel 0 tand 1 are located sequentially at address 0x0000 and 0x0200. Transmit data byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus operation can only write or read in bytes. WRITE TX FIFO BYTE 3 BYTE 2 BYTE 1 BYTE 0 Write n+0 to n+3 FIFO Data n+3 FIFO Data n+2 FIFO Data n+1 FIFO Data n+0 Write n+4 to n+7 FIFO Data n+7 FIFO Data n+6 FIFO Data n+5 FIFO Data n+4 Etc. TABLE 11: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE PCI Bus Data Bit-31 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 Transmit Data Byte n+3 Transmit Data Byte n+2 Transmit Data Byte n+1 Transmit Data Byte n+0 PCI Bus Data Bit-0 Channel 0 to 1 Transmit Data in 32-bit alignment through the Configuration Register Address 0x0100 and 0x0300 THR and RHR Address Locations For CH0 to CH1 (16C550 Compatible) CH0 0x000 Write THR CH0 0x000 Read RHR CH1 0x200 Write THR CH1 0x200 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 |
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