 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HX6408-VNN Datasheet(PDF) 9 Page - Honeywell Solid State Electronics Center |
|
||||||||||||||||||||||||||||||
HX6408-VNN Datasheet(HTML) 9 Page - Honeywell Solid State Electronics Center |
|
|
9 / 11 page  HX6408 Advanced Information 9 www.honeywell.com DYNAMIC ELECTRICAL CHARACTERISTICS Asynchronous Operation The RAM is asynchronous in operation. Read and Write cycles are controlled by NWE, NCS, NSL, and Address signals. Read Operation To perform a valid read operation, both chip select and output enable (NOE) must be low and not sleep (NSL) and write enable (NWE) must be high. The output drivers can be controlled independently by the NOE signal. To perform consecutive read operations, NCS is required to be held continuously low, NSL held continuously high, and the toggling of the addresses will start the new read cycle. It is important to have the address bus free of noise and glitches, which can cause inadvertent read operations. The control and address signals should have rising and falling edges that are fast (<5 ns) and have good signal integrity (free of noise, ringing or steps associated reflections). For an address activated read cycle, NCS and NSL must be valid prior to or coincident with the address edge transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid TAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is TAVAV. When the RAM is operated at the minimum address activated read cycle time, the data outputs will remain valid on the RAM I/O until TAXQX time following the next sequential address transition. To control a read cycle with NCS, all addresses and NSL must be valid prior to or coincident with the enabling NCS edge transition. Address or NSL edge transitions can occur later than the specified setup times to NCS; however, the valid data access time will be delayed. Any address edge transition, which occurs during the time when NCS is low, will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TSHQZ time following a disabling NCS edge transition. To control a read cycle with NSL, all addresses and NCS must be valid prior to or coincident with the enabling NSL edge transition. Address or NCS edge transitions can occur later than the specified setup times to NSL; however, the valid data access time will be delayed. Any address edge transition, which occurs during the time when NSL is high will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TPLQZ time following a disabling NSL edge transition. Write Operation To perform a write operation, both NWE and NCS must be low, and NSL must be high. Consecutive write cycles can be performed by toggling one of the control signals while the other remains in their “write” state (NWE or NCS held continuously low, or NSL held continuously high). At least one of the control signals must transition to the opposite state between consecutive write operations. The write mode can be controlled via three different control signals: NWE, NCS, and NSL. All three modes of control are similar, except the NCS and NSL controlled modes actually disable the RAM during the write recovery pulse. NSL fully disables the RAM decode logic and input buffers for power savings. Only the NWE controlled mode is shown in the table and diagram on the previous page for simplicity; however, each mode of control provides the same write cycle timing characteristics. Thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low. To write data into the RAM, NWE and NCS must be held low and NSL must be held high for at least WLWH/TSLSH/TPHPH time. Any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. The DATA IN must be valid TDVWH time prior to switching high. For consecutive write operations, write pulses (NWE) must be separated by the minimum specified WHWL/TSHSL/TPLPL time. Address inputs must be valid at least TAVWL/TAVSL/TAVPH time before the enabling NWE/NCS/NSL edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of TDVWH/TDVSH/ TDVPL, and an address valid to end of write time of TAVWH/TAVSH/TAVPL also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling NWE/NCS/NSL edge transition must be a minimum of TWHAX/TSHAX/TPLPX time and TWHDX/TSHDX |
Similar Part No. - HX6408-VNN |
|
Similar Description - HX6408-VNN |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
