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XR16L651CM Datasheet(PDF) 3 Page - Exar Corporation |
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XR16L651CM Datasheet(HTML) 3 Page - Exar Corporation |
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3 / 56 page  áç áç áç áç XR16L651 REV. 1.3.0 2.25V TO 5.5V UART WITH 32-BYTE FIFO 3 PIN DESCRIPTIONS NAME PIN #TYPE DESCRIPTION 16 (Intel) or 68 (Motorola) MODE DATA BUS INTERFACE. The PCMODE# pin is connected to VCC. A2 A1 A0 26 27 28 I Address bus lines [2:0] A2:A0 selects internal UART’s configuration registers. D7 D6 D5 D4 D3 D2 D1 D0 4 3 2 48 47 46 45 44 IO Data bus lines [7:0] (bidirectional) IOR# 19 I Input/Output Read (active low) When IM# pin is at logic 0, it selects Intel bus interface and this input is read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], places it on the data bus to allow the host processor to read it on the leading edge. When IM# pin is at logic 1, it selects Motorola bus interface and the IOR# input is not used and it should be connected to GND to minimize supply current. Its function is the same as IOR, except it is active low. Either an active IOR# or IOR is required to transfer data from 651 to CPU during a read operation. If this input is unused in the Intel bus mode (IM# pin is at logic 0), it should be connected to VCC to minimize supply current. IOR 20 I Input/Output Read (active high) Same as IOR# but active high. When IM# pin is at logic 1 for Motorola bus mode, this pin is not used and should be connected to GND to minimize sup- ply current. If this input is unused in the Intel bus mode (IM# pin is at logic 0), it should be connected to GND to minimize supply current. IOW# (R/W#) 16 I Input/Output Write (active low) - Intel bus mode When IM# pin is at logic 0, it selects the Intel bus interface and this input becomes the write strobe (active low). The falling edge instigates the internal write cycle and the trailing edge transfers the data byte on the data bus to an internal register pointed by the address lines [A2:A0]. Its function is the same as IOW, except it is active low. Either an active IOW# or IOW is required to transfer data from 651 to the Intel type CPU during a write operation. If this input is unused (in the Intel bus mode), it should be connected to VCC to min- imize supply current. Read/Write Strobe - Motorola bus mode When IM# pin is at logic 1, it selects Motorola bus interface and this input becomes R/W# signal for read (logic 1) and write (logic 0). IOW 17 I Input/Output Write (active high) Same as IOW# but active high. When IM# pin is at logic 1 for Motorola bus mode, this pin must be connected to GND to allow IOW# input to function cor- rectly. If this input is unused in the Intel bus mode (IM# pin is at logic 0), it should be connected to GND to minimize supply current. |
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