EM39LV088

8M Bits (1Mx8) Flash Memory

SPECIFICATION

This specification is subject to change without further notice. (04.09.2004 V1.0)

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Pin Description

Pin Name

Function

A0–A19

20 addresses

DQ7–DQ0

Data inputs/outputs

CE#

Chip enable

OE#

Output enable

WE#

Write enable

2.7-3.6 volt single power supply

Device ground

NC

Pin not connected internally

Table 1: Pin Description

Device Operation

The EM39LV088 uses Commands to initiate the memory operation functions. The

Commands are written to the device by asserting WE# Low while keeping CE# Low. The

address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data

bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the EM39LV088 is controlled by CE# and OE#. Both have to be Low

for the system to obtain data from the outputs. CE# is used for device selection. When CE#

is high, the chip is deselected and only standby power is consumed. OE# is the output

control and is used to gate data from the output pins. The data bus is in high impedance state

when either CE# or OE# is high. Refer to the Read Cycle Timing Diagram in Figure 1 for

further details.

Byte Program

The EM39LV088 is programmed on a byte-by-byte basis. Before programming, the sector

where the byte is located; must be erased completely. The Program operation is

accomplished in three steps:

The first step is a three-byte load sequence for Software Data Protection.

The second step is to load byte address and byte data. During the Byte Program

operation, the addresses are latched on the falling edge of either CE# or WE#, whichever

occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever

occurs first.

The third step is the internal Program operation which is initiated after the rising edge of

the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated,

will be completed within 20 µs. See Figures 2 and 3 for WE# and CE# controlled

Program operation timing diagrams respectively and Figure 12 for flowchart.