HANBit

HMN4M8DV(N)

URL : www.hbe.co.kr

2

HANBit Electronics Co.,Ltd

Rev. 1.0 (May, 2002)

FUNCTIONAL DESCRIPTION

The HMN4M8DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by

When power is valid, the HMN4M8DV operates as a standard CMOS SRAM. During power -down and power-up cycles,

the HMN4M8DV acts as a nonvolatile memory, automatically protecting and preserving the memory contents.

The HMN4M8DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs

are stable. The later occurring falling edge of /CE or /WE will d etermine the start of the write cycle. The write cycle is

terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. WE

signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled

The HMN4M8DV provides full functional capability for V cc greater than 4.5 V and write protects by 4.37 V nominal.

care” and all outputs are high impedance. As V cc falls below approximately 3 V, the power switching circuit connects the

lithium energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 3.0 volts, the power

switching circuit connects external V cc to the RAM and disconnects the lithium energy source. Normal RAM operation

can resume after Vcc exceeds 4.5 volts.

BLOCK DIAGRAM

PIN DESCRIPTION

/CE : Chip Enable

/WE : Write Enable

/OE : Output Enable

NC : No Connection

/OE

/WE

Power

Lithium

Cell

(1M x 8) x 4

SRAM

Block

CE2

/CE1

/CE

Power – Fail

Control