MU9C4320L ATMCAM

Pin Descriptions

4

Rev. 3

PIN DESCRIPTIONS

Note: Signal names that start with a slash (“/”) are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The

CAM architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer

to the Electrical Characteristics section for more information.

DQ31–0 (Data Bus, Three-state, Common

Input/Output)

The DQ31–0 lines convey data to and from the

ATMCAM. When the /E input is HIGH the DQ31–0 lines

are held in their high-impedance state. The /W input

determines whether data flows to or from the device on the

DQ31–0 lines. The source or destination of the data is

determined by the AC11–0 lines and the /AV line. During

a Write cycle, data on the DQ31–0 lines is registered by

the falling edge of /E.

AC11–0 (Address/Control Bus, Input)

When Hardware control is selected, the AC11–0 lines

convey address or control information to the ATMCAM,

depending on the state of the /AV input. When /AV is

LOW then AC11–0 carry an address; when /AV is HIGH

AC11–0 carry control information. Data on the AC11–0

lines are registered by the falling edge of /E. When

software control is selected, the state of the AC11–0 lines

does not affect the operation of the device.

AA11–0 (Active Address, Output)

The AA11–0 lines convey the CAM Match address, the

VP Table address, the Next Free address, or Random

Access address, depending on the most recent memory

cycle. The /OE input enables the AA11–0 outputs; when

the /OE input is HIGH, the AA11–0 outputs are in their

high-impedance state; when /OE is LOW the AA11–0

lines are active. In a vertically cascaded system after a

Comparison cycle, Write at Next Free Address cycle or

Read/Write

at

Highest-Priority

match,

only

the

highest-priority device will enable its AA11–0 lines,

regardless of the state of the /OE input. In the event of a

mismatch in both CAM array and VP Table after a

Compare cycle, or after a Write at Next Free Address

cycle into an already full system, the lowest-priority

device will drive the AA11–0 lines with all 1s. The

AA11–0 lines are latched when /E is LOW, and are free to

change only when /E is HIGH.

Figure 3: ATMCAM Pinout

ATMCAM

100-Pin TQFP

(Top View)

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

81

31

100

99

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

32

TCLK

TMS

TDI

DQ0

DQ1

DQ2

DQ3

VDD

DQ4

DQ5

DQ6

DQ7

GND

DQ8

DQ9

DQ10

DQ11

VDD

DQ12

DQ13

DQ14

DQ15

GND

GND

GND

AC11

AC10

AC9

AC8

AC7

AC6

VDD

AC5

AC4

AC3

AC2

AC1

AC0

TDO

NC