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ATV5000-30UM-883 Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATV5000-30UM-883 Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 13 page Using The ATV5000 The ATV5000’s simple, regular architecture means that only simple logic compilers are required to configure the device. No layout or route and place are required. These software tools are readily available from companies such as Data I/O Corporation (ABEL ™), Logical Devices (CUPL™), MINC Inc. (PLDes- igner-XL ™), and ISDATA (LOGiC™). The first step in designing a device as complex as the ATV5000 is to partition your design into manageable blocks. These blocks are then allocated proportionally to each of the four quadrants of the ATV5000. Random gates can be described either with boolean equations (a behavioral description) or with a schematic editor. Truth table logic and state machines are best described behaviorially and entered with a text editor. The design is then combined into one ASCII file, which is then submitted to the logic compiler. Compilation, logic reduction, simulation, JEDEC file creation and documentation are then completed by all of the popular compilers. Assignment of signals to pins or buried nodes as well as select- ing the various options of the ATV5000 (such as register clocks and input latches) can be done manually in the design data base file, or an automatic fitter may be used. A logic fitter assigns pins and nodes to make best use of the features in the ATV5000, and frees the designer from being re- quired to learn all of the features of a complex device such as the ATV5000. For further information on fitters for the ATV5000, contact Atmel’s PLD applications department. After correcting any syntax and logic errors discovered by the compiler, the JEDEC file is ready to download to an PLD pro- grammer. These are available from a number of manufacturers. Programmed devices are usually first tested in the programmer with your supplied test vectors. The next step is check out your "custom chip" in the target system. When this hardware debug step is complete, your system is ready to go— all in a matter of hours. ABEL ™, CUPL™, PLDesigner-XL™ and LOGiC™ may be trademarks of others. RANDOM GATES PA RTITION D ESIGN INT O MANAGABLE P IECES S TAT E MACHINES TRUTH TABLES SCHEMATIC EDIT OR TEXT EDIT OR DESIGN DATA BASE (ASCII FILE) TRANSFER JEDEC F ILE AND P ROGRAM COMPILE AND S IMULAT E HARDWARE TEST SHIP IT! E RRORS ? E RRORS ? E RRORS ? E RRORS ? CORRE CT Design Flow Diagram Power Up Reset The registers in the ATV5000 are designed to reset during power up. At a point delayed slightly from VCC crossing 3.8 V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1) The VCC rise must be monotonic, 2) After reset occurs, all input and feedback setup times must be met before driving the clock term high, and 3) The signals from which the clock is derived must remain sta- ble during tPR. Parameter Description Min Typ Max Units tPR Power-Up Reset Time 600 1000 ns ATV5000/L 1-201 |
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