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24LLC02A Datasheet(PDF) 9 Page - Ceramate Technical |
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24LLC02A Datasheet(HTML) 9 Page - Ceramate Technical |
9 / 19 page 24LLC02 2K-Bits Serial EEPROM For Low Power * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Fax:886-3-3521052 Page 9 of 19 Rev 1.0 Dec. 26, 2001 PAGE WRITE OPERATION The 24LLC02 can also perform 16-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 15 additional bytes. The 24LLC02 responds with an ACK each time it receives a complete byte of data (see Figure 1-10). Slave Address Word Address (n) Start A C K A C K Data (n) A C K A C K Data ( ≤ n + 15) Stop A C K Figure 1-10. Page Write Operation The 24LLC02 automatically increments the word address pointer each time it receives a complete data byte. When one byte has been received, the internal word address pointer increments to the next address and the next data byte can be received. If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation, the 24LLC02 word address pointer value “rolls over” and the previously received data is overwritten.If the master transmits less than 16 bytes and generates a stop condition, the 24LLC02 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there is no response to additional requests from the master until the internal write cycle is completed. |
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