Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

V53C1256164VBLT10E Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part # V53C1256164VBLT10E
Description  256Mbit MOBILE SDRAM 2.5 VOLT FBGA PACKAGE 16M X 16
Download  46 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ETC1 [List of Unclassifed Manufacturers]
Direct Link  
Logo ETC1 - List of Unclassifed Manufacturers

V53C1256164VBLT10E Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers

  V53C1256164VBLT10E Datasheet HTML 1Page - List of Unclassifed Manufacturers V53C1256164VBLT10E Datasheet HTML 2Page - List of Unclassifed Manufacturers V53C1256164VBLT10E Datasheet HTML 3Page - List of Unclassifed Manufacturers V53C1256164VBLT10E Datasheet HTML 4Page - List of Unclassifed Manufacturers V53C1256164VBLT10E Datasheet HTML 5Page - List of Unclassifed Manufacturers V53C1256164VBLT10E Datasheet HTML 6Page - List of Unclassifed Manufacturers V53C1256164VBLT10E Datasheet HTML 7Page - List of Unclassifed Manufacturers V53C1256164VBLT10E Datasheet HTML 8Page - List of Unclassifed Manufacturers V53C1256164VBLT10E Datasheet HTML 9Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 46 page
background image
5
V55C2256164VB Rev. 1.0 April 2005
ProMOS TECHNOLOGIES
V55C2256164VB
Description
The V55C2256164VB is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16. The
V55C2256164VB achieves high speed data transfer rates up to 143 MHz by employing a chip architecture
that prefetches multiple bits and then synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of an ex-
ternally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at
higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is
possible depending on burst length, CAS latency and speed grade of the device.
Signal Pin Description
Pin
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
CS
Input
Pulse
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0 - A12
Input
Level
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
• 8M x 16 SDRAM CA0–CA8.
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
BA0,
BA1
Input
Level
Selects which bank is to be active.
DQx
Input
Output
Level
Data Input/Output pins operate in the same manner as on conventional DRAMs.
LDQM
UDQM
Input
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
VCC, VSS
Supply
Power and ground for the input buffers and the core logic.
VCCQ
VSSQ
Supply
Isolated power supply and ground for the output buffers to provide improved noise
immunity.


Similar Part No. - V53C1256164VBLT10E

ManufacturerPart #DatasheetDescription
logo
Mosel Vitelic, Corp
V53C104 MOSEL-V53C104 Datasheet
1Mb / 19P
   HIGH PERFORMANCE, LOW POWER 256K X 4 BIT FAST PAGE MODE CMOS DYNAMIC RAM
V53C104A MOSEL-V53C104A Datasheet
1Mb / 17P
   HIGH PERFORMANCE, LOW POWER 256K X 4 BIT FAST PAGE MODE CMOS DYNAMIC RAM
V53C104AK MOSEL-V53C104AK Datasheet
1Mb / 17P
   HIGH PERFORMANCE, LOW POWER 256K X 4 BIT FAST PAGE MODE CMOS DYNAMIC RAM
V53C104AK-100 MOSEL-V53C104AK-100 Datasheet
1Mb / 17P
   HIGH PERFORMANCE, LOW POWER 256K X 4 BIT FAST PAGE MODE CMOS DYNAMIC RAM
V53C104AK-100L MOSEL-V53C104AK-100L Datasheet
1Mb / 17P
   HIGH PERFORMANCE, LOW POWER 256K X 4 BIT FAST PAGE MODE CMOS DYNAMIC RAM
More results

Similar Description - V53C1256164VBLT10E

ManufacturerPart #DatasheetDescription
logo
Emerging Memory & Logic...
EMD56164P EMLSI-EMD56164P Datasheet
770Kb / 45P
   256M: 16M x 16 Mobile DDR SDRAM
logo
Mosel Vitelic, Corp
V54C3256164VALT6 MOSEL-V54C3256164VALT6 Datasheet
838Kb / 52P
   256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
V54C3256 MOSEL-V54C3256 Datasheet
853Kb / 52P
   256Mbit SDRAM 3.3 VOLT, TSOP II / SOC BGA / WBGA PACKAGE 16M X 16, 32M X 8, 64M X 4
V54C3256164VBUC MOSEL-V54C3256164VBUC Datasheet
651Kb / 45P
   LOW POWER 256Mbit SDRAM 3.3 VOLT, 54-BALL SOC BGA 54-PIN TSOPII 16M X 16
logo
Samsung semiconductor
K4S560432B SAMSUNG-K4S560432B Datasheet
130Kb / 11P
   256Mbit SDRAM 16M x 4bit x 4 Banks Synchronous DRAM LVTTL
K4S560432A SAMSUNG-K4S560432A Datasheet
127Kb / 10P
   256Mbit SDRAM 16M x 4bit x 4 Banks Synchronous DRAM LVTTL
logo
Mosel Vitelic, Corp
V826516K04S MOSEL-V826516K04S Datasheet
159Kb / 13P
   2.5 VOLT 16M x 64 HIGH PERFORMANCE UNBUFFERED DDR SDRAM MODULE
logo
Integrated Silicon Solu...
IS43LR32640A ISSI-IS43LR32640A Datasheet
1Mb / 43P
   16M x 32Bits x 4Banks Mobile DDR SDRAM
logo
Hynix Semiconductor
H5MS5122DFR HYNIX-H5MS5122DFR Datasheet
2Mb / 62P
   Mobile DDR SDRAM 512Mbit (16M x 32bit)
logo
Emerging Memory & Logic...
EMD12324PV EMLSI-EMD12324PV Datasheet
938Kb / 46P
   512M: 16M x 32 Mobile DDR SDRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com