HANBit

HFDOM44P-xxxSx

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HANBit Electronics Co., Ltd.

REV 1.0 (August.2002)

Table 3.3 IDE Mode I/O Write Timing

Parameter

Symbol

IEEE Symbol

Min. ns

Max. ns

Data Setup before IOWR

tsu(IOWR)

tDVIWH

60

Data Hold following IOWR

th(IOWR)

tlWHDX

30

IOWR Width Time

twI(OWR)

tlWLIWH

165

Address Setup before IOWR

tsuA(IOWR)

tAVIWL

70

Address Hold following IOWR

thA(IOWR)

tlWHAX

20

CE Setup before IOWR

tsuCE(IOWR)

tELIWL

5

CE Hold following IOWR

thCE(IOWR)

tlWHEH

20

IOIS16 Delay Falling from Address

tdfIOIS16(ADR)

tAVISL

35

IOIS16 Delay Rising from Address

tdrIOIS16(ADR)

tAVISH

35

NOTE: The maximum load on -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum

time from -WAIT high to -IOWR high is 0nsec, but minimum -IOWR width must still be met.

A0-A10

-CE

-IOWR

-IOIS16

Din

Figure 3.2 IDE Mode I/O Write Timing Example