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DOM40S3V256 Datasheet(PDF) 10 Page - Hanbit Electronics Co.,Ltd |
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DOM40S3V256 Datasheet(HTML) 10 Page - Hanbit Electronics Co.,Ltd |
10 / 29 page HANBit HFDOM40S3Vxxx URL:www.hbe.co.kr 10 / 29 HANBit Electronics Co., Ltd. Rev. 1.0 (July, 2004) D7 D6 D5 D4 D3 D2 D1 D0 BUSY RDY DWF DSC DRQ CORR 0 ERR Status & Alternate Status Register Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. Bit 6 (DRDY): DRDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a command. Bit 5 (DWF): This bit, if set, indicates a write fault has occurred. Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready. Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires the information to be transferred either to or from the host through the Data register. Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation. Bit 1 (IDX): This bit is always set to 0. Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is recommended that media access commands (such as Read Sectors and Write Sectors) that end with an error condition should have the address of the first sector in error in the command block registers. 9) Device Control Register( Address – 3F6h[376h]; Offset Eh) This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows: D& D6 D5 D4 D3 D2 D1 D0 X X X X 1 SW Rst -IEn 0 Device Control Register Bit 7: this bit is an X (don’t care). Bit 6: this bit is an X (don’t care). Bit 5: this bit is an X (don’t care). Bit 4: this bit is an X (don’t care). Bit 3: this bit is ignored by the CompactFlash Storage Card. Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers (4.3.2 to 4.3.5) as a hardware Reset does. The Card remains in Reset until this bit is reset to ‘0.’ Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, The interrupts from the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the Configuration and Status Register. This bit is set to 0 at power on and Reset. Bit 0: this bit is ignored by the CompactFlash Storage Card. 10) Card (Drive) Address Register(Address 3F7h[377h]; Offset Fh) This register is provided for compatibility with the AT disk drive interface. It is recommended that this register not be mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined as follows: D7 D6 D5 D4 D3 D2 D1 D0 X -WTG -HS3 -HS2 -HS1 -HS0 -nDS1 -nDS0 Card (Drive) Address Register Bit 7: this bit is in High Imoedence.. |
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