7

COMMERCIALTEMPERATURERANGE

IDT72V3631/72V3641/72V3651

3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36

AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF

SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

IDT72V3631L15

IDT72V3631L20

IDT72V3641L15

IDT72V3641L20

IDT72V3651L15

IDT72V3651L20

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Clock Frequency, CLKA or CLKB

–

66.7

–

50

MHz

Clock Cycle Time, CLKA or CLKB

15

–

20

–

ns

Pulse Duration, CLKA or CLKB HIGH

6

–

8

–

ns

Pulse Duration, CLKA or CLKB LOW

6

–

8

–

ns

Setup Time, A0-A35 before CLKA

↑ and B0-B35

5

–

6

–

ns

before CLKB

↑

Setup Time, ENA to CLKA

↑;ENBtoCLKB↑

5–

6

–

ns

Setup Time,

CSA, W/RA, and MBA to CLKA

↑;

7

–

7.5

–

ns

CSB, W/RB, and MBB to CLKB

↑

Setup Time, RTM and RFM to CLKB

↑

6

–

6.5

–

ns

Setup Time,

RST LOW before CLKA

↑

5–

6

–

ns

or CLKB

Setup Time, FS0 and FS1 before

RST HIGH

9

–

10

–

ns

Setup Time, FS0/SD before CLKA

↑

5–

6

–

ns

Setup Time, FS1/

SEN before CLKA

↑

5–

6

–

ns

Hold Time, A0-A35 after CLKA

↑ and B0-B35

0.5

–

0.5

–

ns

afterCLKB

↑

Hold Time, ENA after CLKA

↑;ENBafterCLKB↑

0.5

–

0.5

–

ns

Hold Time,

CSA, W/RA, and MBA after CLKA

↑;

0.5

–

0.5

–

ns

CSB, W/RB, and MBB after CLKB

↑

Hold Time, RTM and RFM after CLKB

↑

0.5

–

0.5

–

ns

Hold Time,

RST LOW after CLKA

5–

6

–

ns

Hold Time, FS0 and FS1 after

RST HIGH

0

–

0

–

ns

Hold Time, FS1/

SEN HIGH after RST HIGH

0

–

0

–

ns

Hold Time, FS0/SD after CLKA

↑

0–

0

–

ns

Hold Time, FS1/

SEN after CLKA

↑

0–

0

–

ns

Skew Time, between CLKA

↑ andCLKB↑

9–

11

–

ns

for OR and IR

Skew Time, between CLKA

↑ andCLKB↑

12

–

16

–

ns

for

AE and AF

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Only applies when serial load method is used to program flag Offset registers.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

4. Design simulated, not tested.