8

COMMERCIALTEMPERATURERANGE

IDT72V3631/72V3641/72V3651

3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36

AC ELECTRICAL CHARACTERISTICS

IDT72V3631L15

IDT72V3631L20

IDT72V3641L15

IDT72V3641L20

IDT72V3651L15

IDT72V3651L20

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Clock Frequency, CLKA or CLKB

–

66.7

–

50

MHz

Access Time, CLKB

↑toB0-B35

2

10

2

12

ns

Propagation Delay Time, CLKA

↑ to IR

1

8

1

10

ns

Propagation Delay Time, CLKB

↑to OR

1

8

1

10

ns

Propagation Delay Time, CLKB

↑ to AE

18

1

10

ns

Propagation Delay Time, CLKA

↑ to AF

18

1

10

ns

Propagation Delay Time, CLKA

↑ to MBF1

08

0

10

ns

LOW or

MBF2 HIGH and CLKB

↑ to MBF2

LOW or

MBF1 HIGH

Propagation Delay Time, CLKA

210

2

12

ns

and CLKB

Propagation Delay Time, MBB to B0-B35 Valid

2

10

2

12

ns

Propagation Delay Time,

RST LOW to AE LOW

1

15

1

20

ns

and

AF HIGH

Enable Time,

CSA and W/RA LOW to A0-A35

2

10

2

12

ns

Active and

CSB LOW and W/RB HIGH to

B0-B35 Active

Disable Time,

CSA or W/RA HIGH to A0-A35

1

8

1

10

ns

at high impedance and

CSB HIGH or W/RB

LOW to B0-B35 at high impedance

NOTES:

1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.

2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.