7 / 13 page
U631H256
7
March 31, 2006
STK Control #ML0043
Rev 1.0
No.
STORE Cycle Inhibit and
Automatic Power Up RECALL
Symbol
Min.
Max.
Unit
Alt.
IEC
24 Power Up RECALL Durationk
tRESTORE
650
μs
Low Voltage Trigger Level
VSWITCH
4.0
4.5
V
Nonvolatile Memory Operations
k:
tRESTORE starts from the time VCC rises above VSWITCH.
STORE Cycle Inhibit and Automatic Power Up RECALL
VCC
5.0 V
STORE inhibit
Power Up
VSWITCH
tRESTORE
RECALL
(24)
t
Software Mode Selection
E
W
A13 - A0
(hex)
Mode
I/O
Power
Notes
L
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
ICC2
l, m
l, m
l, m
l, m
l, m
l, m
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l, m
l:
The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
m: While there are 15 addresses on the U631H256, only the lower 14 are used to control software modes.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
