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STCCP27A Datasheet(PDF) 9 Page - STMicroelectronics |
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STCCP27A Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 19 page  STCCP27A Electrical characteristics 9/19 Table 7. Switching characteristics (RT = 100Ω ± 1%, CL = 10pF, over recommended operating conditions unless otherwise noted. Typical values are referred to TA = 25°C and VDD = 2.8V, VL = 1.8V) Note: 1 50% VDIN to 50% VDOUT Table 8. Capacitive characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit tr Rise time LVTTL Output voltage (10% to 90%) 3.1 4.0 ns tf Fall time LVTTL output voltage (90% to 10%) 2.0 4.0 ns tr I/O Rise time I2C input/output voltage (20% to 80%) 320 ns tf I/O Fall time I2C input/output voltage (80% to 20%) 20 ns tpLH Propagation delay time (CLK to V- SYNC, H-SYNC) (low to high) 6.5 8.5 ns tpHL Propagation delay time (CLK to V- SYNC, H-SYNC) (high to low) 6.5 8.5 ns tpLH Propagation delay time (CLK to D1-D8) (low to high) 6.5 8.5 ns tpHL Propagation delay time (CLK to D1-D8) (high to low) 6.5 8.5 ns tpLH Propagation delay time I2C input/output voltage (50% to 50%) (Low to High) 100 ns tpHL Propagation delay time I2C input/output voltage (50% to 50%) (High to Low) 10 ns tEN Enable delay time (EN to V-SYNC, H-SYNC: tPZL, tPZH) trEN = 2.0ns (10% to 90%) tfEN = 2.0ns (90% to 10%) 20 µs tDIS Disable delay time (EN to V- SYNC, H-SYNC: tPLZ, tPHZ) trEN = 2.0ns (10% to 90%) tfEN = 2.0ns (90% to 10%) 1000 ns fOPR Operating frequency trD,CLK = 400ps (10% to 90%) tfD,CLK = 400ps (90% to 10%) VCM D,CLK = 0.9V, VDD,CLK = 150mV 1416 MHz TCLK Clock Period 2.4 1000 ns tSUD-CLK Setup time (D to CLK) (low to high or high to low vs positive CLK edge) (note 1) (see fig. 6) 0.6 ns tHCLK-D Hold time (CLK to D) (positive CLK edge to D) (note 1) (see fig. 6) 1.0 ns Symbol Parameter Test condition Value Unit VDD (V) TA = 25°C Min. Typ. Max. CIN Input Capacitance (SYNC_SEL, EN) 2.65 to 3.6 VL = 1.65V to 1.95V, VI = GND or VDD 3.5 pF |
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