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APW7035AKC-TU Datasheet(PDF) 5 Page - Anpec Electronics Coropration |
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APW7035AKC-TU Datasheet(HTML) 5 Page - Anpec Electronics Coropration |
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5 / 11 page  Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2001 APW7035 www.anpec.com.tw 5 Functional Pin Description cont. NC (Pin 3, Pin 4 and Pin 5) No Connect. (APW7035-12,19) PGOOD (Pin 5) PGOOD is an open drain output used to indicate the status of the output voltages. This pin is pulled low when the synchronous regulator output is not within ±10% of the DAC reference voltage or Linear regula- tor outputs are below under-voltage thresholds. (APW7035-A,B,C,D) VID2 , VID1 , VID0 (Pin 3,4 and 5) VID0-2 are the TTL-compatible input pins to the 3-bit DAC. The logic states of these three pins program the internal voltage reference (DAC). The level of DAC sets the microprocessor core converter output volt- age , as well as the corresponding PGOOD and OVP thresholds. (APW7035-A,B,C,D) SD (Pin 6) The pin shuts down all the outputs. A TLL-compatible , logic lebel high signal applied at this pin immedi- ately discharges the soft-start capacitor , disbling all the output. VSEN2 (Pin 7) Connect this pin to a resistor divider to set the linear regulator (FBVDDQ) output voltage. SS (Pin 8) Connect a capacitor from this pin to ground. This capacitor , along with an internal 28 µA current source , sets the soft-start interval of the converter. NC (Pin 9 and Pin12) No Connection. VAUX (Pin 10) This pin provides boost current for the linear regulator’s output drives in the event bipolar NPN transistors (instead of N-channel MOSFETs) are employed as pass elements. The voltage at this pin is monitored for power-on reset purposes. GND (Pin 11) Signal ground for the IC. All voltage levels are mea- sured with respect to this pin. FB and COMP (Pin 13, and 14) COMP and FB are the available external pins of the PWM converter error amplifier. The FB pin is the inverting input of the error amplifier. Similarly , the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter. VSEN1 (Pin 15) This pin is connected to the PWM converter’s output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for over- voltage protection. OCSET (Pin 16) Connect a resistor from this pin to the drain of the respective upper MOSFET. This resistor , an inter- nal 200 µA current source , and the upper MOSFET’s on-resistance set the converter over-current trip point. An over-current trip cycles the soft-start function. The voltage at this pin is monitored for power-on reset (POR) purposes and pulling this pin low with an open drain device will shutdown the IC. PGND (Pin 17) This is the power ground connection. Tie the syn- chronous PWM converter’s lower MOSFET source to this pin. LGATE (Pin 18) Connect LGATE to the PWM converter’s lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. |
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