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APL5330KE-TR Datasheet(PDF) 11 Page - Anpec Electronics Coropration |
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APL5330KE-TR Datasheet(HTML) 11 Page - Anpec Electronics Coropration |
11 / 17 page Copyright © ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 APL5330 www.anpec.com.tw 11 0 5 10 15 20 25 10 100 1000 Application Information (Cont.) Output Capacitor The APL5330 requires a proper output capacitor to maintain stability and improve transient response. The APL5330 can work stably with wide range of capacitance and ESR (equivalent series resistance). A low-ESR solid tantalum, aluminum electrolytic or ceramic output capacitor works extremely well and provides good transient response and stability over temperature. The output capacitors also reduce the slew rate of load current and help the APL5330 to minimize variations of the output voltage. For this purpose, the low-ESR capacitors which depend on the step size and slew rate of load current are recommended. Input Capacitor The input capacitors of VCNTL and VIN pins are not required for stability but for supplying surge current during large load transients. This will prevent the input rail from dropping and improve the performance of the APL5330. The parasitic inductors between voltage sources or bulk capacitors and the power input pins will limit the slew rate of the surge currents during large load transients, resulting in voltage drop at VIN and VCNTL pins. Stable Region Capacitance (uF) For VCNTL pin, a capacitor of 1 µF (ceramic chip capacitor) or greater (aluminum electrolytic capacitor) is recommended. For VIN pin, an aluminum electrolytic capacitor (>47 µF) is recommended. It is not necessary to use low-ESR capacitors. Layout and Thermal Consideration The input capacitors for VIN and VCNTL pins are normally placed near each pin for good performances. Ceramic decoupling capacitors of output must be placed as close to the load to reduce the parasitic inductance of traces. It is also recommended to place the APL5330 and output capacitors near the load for good load regulation and load transient response. Please connect the negative pins of the input and output capacitors and the GND pin of the APL5330 to the power ground plane of the load. See figure 1. The SOP-8-P utilizes a bottom thermal pad to minimize the thermal resistance of the package and make the package suitable for high current applications. The thermal pad is soldered to the top ground pad connected to the internal or bottom ground plane by several vias. The printed circuit board (PCB) forms a heat sink and dissipates most of the heat into ambient air. It is recommended that the vias have proper size to retain solder and help heat conduction. Thermal resistance consists of two main elements, θJC (junction-to-case thermal resistance) and θCA (case-to-ambient thermal resistance). θJC is specified from the IC junction to the bottom of the thermal pad directly below the die. θCA is the resistance from the bottom of thermal pad to the ambient air and it includes θCS (case-to-sink thermal resistance) and θSA (sink-to- ambient thermal resistance). The specified path for heat flow is the lowest resistance path and it dissipates majority of the heat to the ambient air. Typically, θCA is the dominant thermal resistance. Therefore, enlarging |
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