NB4N11M datasheet(2/11 Pages) ONSEMI

Part #	NB4N11M

Description	3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator

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Manufacturer	ONSEMI [ON Semiconductor]

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NB4N11M

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2

Figure 2. Pinout (Top View) and Logic Diagram

1

2

3

4

5

6

7

8

D

VEE

VCC

Q0

D

Q1

Q0

Table 1. Pin Description

Name

I/O

Description

1

Q0

CML Output

Noninverted differential output. Typically receiver terminated with 50 W

resistor to VTT. Open collector CML outputs must be terminated to VTT at

powerup.

2

Q0

CML Output

Inverted differential output. Typically receiver terminated with 50 W resistor

to VTT. Open collector CML outputs must be terminated to VTT at powerup.

3

Q1

CML Output

Noninverted differential output. Typically receiver terminated with 50 W

resistor to VTT. Open collector CML outputs must be terminated to VTT at

powerup.

4

Q1

CML Output

Inverted differential output. Typically receiver terminated with 50 W resistor

to VTT. Open collector CML outputs must be terminated to VTT at powerup.

5

VEE

−

Negative supply voltage.

6

D

LVPECL, CML, HSTL,

LVCMOS, LVDS, LVTTL Input

Inverted differential input.

7

D

LVPECL, CML, HSTL,

LVCMOS, LVDS, LVTTL Input

Noninverted differential input.

8

VCC

−

Positive supply voltage.

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