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PEEL22CV10ASI-7L Datasheet(PDF) 3 Page - Anachip Corp |
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PEEL22CV10ASI-7L Datasheet(HTML) 3 Page - Anachip Corp |
3 / 10 page Anachip Corp. www.anachip.com.tw Rev. 1.0 Dec 16, 2004 3/10 Function Description The PEEL™22CV10A implements logic functions as sum- of-products expressions in a programmable-AND/ fixed-OR logic array. User-defined functions are created by program- ming the connections of input signals into the array. User- configurable output structures in the form of I/O macrocells further increase logic flexibility. Architecture Overview The PEEL™22CV10A architecture is illustrated in the block diagram of Figure 2. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs for creation of logic functions. At the core of the device is a programmable elec- trically-erasable AND array which drives a fixed OR array. With this structure, the PEEL™22CV10A can implement up to 10 sum-of-products logic expressions. Associated with each of the 10 OR functions is an I/O mac- rocell which can be independently programmed to one of 4 different configurations. The programmable macrocells allow each I/O to create sequential or combinatorial logic functions with either active-high or active-low polarity. AND/OR Logic Array The programmable AND array of the PEEL™22CV10A (shown in Figure 3) is formed by input lines intersecting product terms. The input lines and product terms are used as follows: 44 Input Lines: 24 input lines carry the true and complement of the signals applied to the 12 input pins 20 additional lines carry the true and complement values of feedback or input signals from the 10 I/Os 132 product terms: 120 product terms (arranged in 2 groups of 8, 10, 12, 14 and 16) used to form logical sums 10 output enable terms (one for each I/O) 1 global synchronous present term 1 global asynchronous clear term At each input-line/product-term intersection there is an EEPROM memory cell which determines whether or not there is a logical connection at that intersection. Each prod- uct term is essentially a 44-input AND gate. A product term which is connected to both the true and complement of an input signal will always be FALSE, and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a “don’t care” state exists and that term will always be TRUE. When programming the PEEL™22CV10A, the device programmer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array. The device is then configured to perform the user-defined function by programming selected connections in the AND array. (Note that PEEL™ device programmers automatically program the connections on unused product terms so that they will have no effect on the output function.) Variable Product Term Distribution The PEEL™22CV10A provides 120 product terms to drive the 10 OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14 and 16 to form logical sums (see Figure 3). This distribution allows opti- mum use of device re-sources. Programmable I/O Macrocell The output macrocell provides complete control over the architecture of each output. The ability to configure each output independently permits users to tailor the configura- tion of the PEEL™22CV10A to the precise requirements of their designs. Macrocell Architecture Each I/O macrocell, as shown in Figure 4, consists of a D- type flip-flop and two signal-select multiplexers. The config- uration of each macrocell is determined by the two EEPROM bits controlling these multiplexers (refer to Table 1). These bits determine output polarity and output type (registered or non-registered). Equivalent circuits for the four macro-cell configurations are illustrated in Figure 5. Output Type The signal from the OR array can be fed directly to the out- put pin (combinatorial function) or latched in the D-type flip- flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the glo- bal preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear term will set Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset. Output Polarity Each macrocell can be configured to implement active-high or active-low logic. Programmable polarity eliminates the need for external inverters. Output Enable The output of each I/O macrocell can be enabled or dis- abled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the I/O pin. Otherwise, the output buffer is driven into the high-impedance state. Under the control of the output enable term, the I/O pin can function as a dedicated input, a dedicated output, or a bi- directional I/O. Opening every connection on the output |
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