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PEEL18LV8ZT-35L Datasheet(PDF) 5 Page - Anachip Corp |
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PEEL18LV8ZT-35L Datasheet(HTML) 5 Page - Anachip Corp |
5 / 10 page Anachip Corp. www.anachip.com.tw Rev. 1.0 Dec 16, 2004 5/10 switching long enough to trigger the next power-down. (Note that the tPD is approximately 5 ns. slower on the first transition from sleep mode.) As a result of the "Zero-Power" feature, significant power savings can be realized for combinatorial or sequential operations when the inputs or clock change at a modest rate. See Figure 6. When the PEEL18LV8Z is powered up, a built-in feature holds the outputs in tri-state until Vcc reaches 2.2V. This prevents output transitions during power-up. Figure 5 - Equivalent Circuits for the twelve configurations of the PEEL18LV8Z I/O Macrocell Configuration # A B C D Input/Feedback Select Output Select 1 0 0 1 0 Active Low 2 1 0 1 0 Register Active High 3 0 1 0 0 Active Low 4 1 1 0 0 Bi-directional I/O Combinatorial Active High 5 0 0 1 1 Active Low 6 1 0 1 1 Register Active High 7 0 1 1 1 Active Low 8 1 1 1 1 Combinatorial Feedback Combinatorial Active High 9 0 0 0 0 Active Low 10 1 0 0 0 Register Active High 11 0 1 1 0 Active Low 12 1 1 1 0 Register Feedback Combinatorial Active High |
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