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MAXQ3210-EMX Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAXQ3210-EMX Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 28 page In-Application Programming: The in-application programming feature allows the microcontroller to modify its own program memory from its application software. This allows on-the-fly software updates in mission-critical applications that cannot afford downtime. Alternatively, it allows the application to develop custom loader software that can operate under the control of the application software. The utility ROM contains user-accessible programming functions that erase and program memory. These functions are described in detail in the user’s guide for this device. Register Set Most functions of the device are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and address- ing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU, accu- mulator registers, data pointers, interrupt vectors and control, and stack pointer. The peripheral registers define additional functionality that may be included by different products based on the MAXQ architecture. This functionality is broken up into discrete modules so that only the features required for a given product need to be included. The following tables show the MAXQ3210 register set. Note that the accumulators are 8 bits wide for this device. Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator ____________________________________________________________________ 11 Table 1. System Register Map Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register is 16 bits wide. Registers in module AP are bit addressable. MODULE NAME (BASE SPECIFIER) REGISTER INDEX AP (8h) A (9h) PFX (Bh) IP (Ch) SP (Dh) DPC (Eh) DP (Fh) 0xh AP A[0] PFX[0] IP —— — 1xh APC A[1] PFX[1] — SP —— 2xh — A[2] PFX[2] — IV —— 3xh — A[3] PFX[3] — — Offs DP0 4xh PSF A[4] PFX[4] —— DPC — 5xh IC A[5] PFX[5] —— GR — 6xh IMR A[6] PFX[6] — LC0 GRL — 7xh — A[7] PFX[7] — LC1 BP DP1 8xh SC A[8] — — — GRS — 9xh — A[9] — — — GRH — Axh — A[10] — — — GRXL — Bxh IIR A[11] — — — BP[offs] — Cxh — A[12] — — — — — Dxh — A[13] — — — — — Exh CKCN A[14] — — — — — Fxh WDCN A[15] — — — — — |
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