DS25LV02: Low-Voltage 1024-Bit EPROM

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step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master

performs this simple three-step routine on each bit location of the net address. After one complete pass through all

64 bits, the bus master knows the address of one device. The remaining devices can then be identified on

additional iterations of the process. Refer to Chapter 5 of the Book of DS19xx iButton Standards for a

I/O SIGNALING

The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the

DS25LV02 are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and

read data. The bus master initiates all these types of signaling except the presence pulse.

The initialization sequence required to begin any communication with the DS25LV02 is shown in Figure 5. A

presence pulse following a reset pulse indicates that the DS25LV02 is ready to accept a net address command.

mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ

Figure 5. 1-Wire Initialization Sequence

WRITE-TIME SLOTS

A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level to a logic-low

a 1

write 0 occurs. The sample window is illustrated in Figure 6. For the bus master to generate a write-1 time slot, the

write time slot. For the host to generate a write-0 time slot, the bus line must be pulled low and held low for the

duration of the write-time slot.

READ-TIME SLOTS

A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level.

The bus master must keep the bus line low for at least 1

ms and then release it to allow the DS25LV02 to present

read-time slot, the DS25LV02 releases the bus line and allows it to be pulled high by the external pullup resistor. All

the timing specifications in the Electrical Characteristics table for more information.

PACK+

PACK-

LINE TYPE LEGEND:

BUS MASTER ACTIVE LOW

SLAVE ACTIVE LOW

RESISTOR PULLUP

BOTH BUS MASTER AND

SLAVE ACTIVE LOW

DQ