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CY7C441-12JC Datasheet(PDF) 2 Page - Cypress Semiconductor

Part # CY7C441-12JC
Description  Clocked 512 x 9, 2K x 9 FIFOs
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C441-12JC Datasheet(HTML) 2 Page - Cypress Semiconductor

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CY7C441
CY7C443
Document #: 38-06032 Rev. *A
Page 2 of 15
Maximum Ratings[1](Above which the useful life
may be impaired. For user guidelines, not test-
ed.)
Storage Temperature .................................–65
°C to +150°C
Ambient Temperature with
Power Applied.............................................–55
°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Output Current into Outputs (LOW) .............................20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... > 200 mA
Selection Guide
7C441–12
7C443–12
7C441–14
7C443–14
7C441–20
7C443–20
7C441–30
7C443–30
Maximum Frequency (MHz)
83.3
71.4
50
33.3
Maximum Access Time (ns)
9
10
15
20
Minimum Cycle Time (ns)
12
14
20
30
Minimum Clock HIGH Time (ns)
5
6.5
9
12
Minimum Clock LOW Time (ns)
5
6.5
9
12
Minimum Data or Enable Set-Up (ns)
4
5
6
7
Minimum Data or Enable Hold (ns)
0
0
0
0
Maximum Flag Delay (ns)
9
10
15
20
Maximum Current (mA)
Commercial
140
140
120
100
Military/Industrial
150
150
130
110
Selection Guide (continued)
CY7C441
CY7C443
Density
512 x 9
2,048 x 9
Package
32-Pin PLCC
32-Pin PLCC
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0
°C to +70°C
5V
± 10%
Industrial
–40
°C to +85°C
5V
± 10%
Pin Definitions
Signal Name
I/O
Description
D0–8
I
Data Inputs: when the FIFO is not full and ENW is active, CKW (rising edge) writes data (D0 – D8)
into the FIFO’s memory
Q0–8
O
Data Outputs: when the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q0
Q8) out of the FIFO’s memory
ENW
I
Enable Write: enables the CKW input
ENR
I
Enable Read: enables the CKR input
CKW
I
Write Clock: the rising edge clocks data into the FIFO when ENW is LOW and updates the Almost
Full flag state
CKR
I
Read Clock: the rising edge clocks data out of the FIFO when ENR is LOW and updates the Almost
Empty and Empty flag states
F1
O
Flag 1: is used in conjunction with Flag 2 to decode which state the FIFO is in (see Table 1)
F2
O
Flag 2: is used in conjunction with Flag 1 to decode which state the FIFO is in (see Table 1)
MR
I
Master Reset: resets the device to an empty condition


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