CY7C441
CY7C443
Document #: 38-06032 Rev. *A
Page 11 of 15
whether or not to include the write when the flag is updated by
CKR is arbitrary.
The update cycle for non-boundary flags (Almost Empty, Al-
most Full) is different from that used to update the boundary
flag (Empty). Both operations are described below.
Boundary Flag (Empty)
The Empty flag is synchronized to the CKR signal. The Empty
flag can only be updated by a clock pulse on the CKR pin. An
empty FIFO that is written to will be described with an Empty
flag state until a clock pulse is presented on the CKR pin.
When making the transition from Empty to Almost Empty (or
Empty to Intermediate or Empty to Almost Full), a clock cycle
on the CKR is necessary to update the flags to the current
state. Such a state (flags displaying empty even though data
has been written to the FIFO) would require two read cycles to
read data out of FIFO. The first read serves only to update the
flags to the Almost Empty, Intermediate, or Almost Full state,
and the second read outputs the data. This first read cycle is
known as the latent or flag update cycle because it does not
affect the data in the FIFO or the count (number of words in
FIFO). It simply deasserts the Empty flag. The flags are updat-
ed regardless of the ENR state. Therefore the update occurs
even when ENR is deasserted (HIGH) so that a valid read is
not necessary to update the flags to correctly describe the
FIFO. With a free-running clock connected to CKR, the flag
updates with each cycle.
Table 2 shows sample operations
that update the Empty flag.
Although a Full flag is not supplied externally on the
CY7C441/CY7C443, a Full flag exists internally. The operation
of the FIFO at the Full boundary is analogous to its operation
at the Empty boundary. See the text section “Boundary Flags
(Full)” in the CY7C451/CY7C453 datasheet.
Non-Boundary Flags (Almost Empty, Almost Full)
The flag status pins, F1 and F2, exhibit the Almost Empty sta-
tus when both the CY7C441 and the CY7C443 contain 16
words or less. The Almost Full Flag becomes active when the
FIFO contains 16 or less empty locations. The CY7C441 be-
comes Almost Full when it contains 496 words. The CY7C443
becomes Almost Full when it contains 2032 words. The Almost
Empty flag (like the Empty flag) is synchronous to the CKR
signal, whereas the Almost Full flag is synchronous to the
CKW signal. Non-boundary flags employ flag update cycles
similar to the boundary flag latent cycles in order to update the
FIFO state. For example, if the FIFO just reaches the Almost
Empty state (16 words) and then two words are written, a read
clock (CKR) will be required to update the flags to the Interme-
diate state. However, unlike the boundary (Empty) flag’s up-
date cycle, the state of the enable pin (ENR in this case) af-
fects the operation. Therefore, ENR set-up (tSEN) and hold
(tHEN) times must be met. If ENR is asserted (ENR=LOW) dur-
ing the latent cycle, the count and data update in addition to
F1 and F2. If ENR is not active (ENR=1) during the flag update
cycle, only the flag is updated.
The same principles apply for updating the flags when a tran-
sition from the Almost Full to the Intermediate state occurs. If
the CY7C443 just reaches the Almost Full state (2032 words)
and then two words are read, a write clock (CKW) will be re-
quired to update the flag to the Intermediate state. If ENW is
LOW during the flag update cycle, the count and data update
in addition to the flags. If ENW is HIGH, only the flag is updat-
ed. Therefore, ENW set-up (tSEN) and hold (tHEN) times must
be met. Tables 3 and 4 show examples for a sequence of op-
erations that affect the Almost Empty and Almost Full flags,
respectively.
Width Expansion
The CY7C441/3 can be expanded in width to provide word
width greater than 9 in increments of 9. During width expan-
sion mode, all control inputs are common. When the FIFO is
being read near the Empty boundary, it is important to note that
both sets of flags should be checked to see if they have been
updated to the Not Empty condition on all devices.
Checking all sets of flags is critical so that data is not read from
the FIFOs “staggered” by one clock cycle. This situation could
occur when the first write to an empty FIFO and a read are very
close together. If the read occurs less than tSKEW2 after the first
write to two width expanded devices (A and B), device A may
go Almost Empty (read recognized as flag update) while de-
vice B stays Empty (read ignored).The first write occurs be-
cause a read within tSKEW2 of the first write is only guaranteed
to be either recognized or ignored, but which of the two is not
guaranteed. The next read cycle outputs the first half of the
first word on device A while device B updates its flags to Al-
most Empty. Subsequent reads will continue to output “stag-
gered” data assuming more data has been written to the
FIFOs.
In the width expansion configuration, any of the devices’ flags
may be monitored for the composite Almost Full status.
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