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HDD128M72D18RPW-13B Datasheet(PDF) 5 Page - Hanbit Electronics Co.,Ltd |
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HDD128M72D18RPW-13B Datasheet(HTML) 5 Page - Hanbit Electronics Co.,Ltd |
5 / 14 page HANBit HDD128M72D18RPW URL : www.hbe.co.kr 5 HANBit Electronics Co.,Ltd. REV 1.0 (January. 2005) Absolute Maximum Ratings PARAMETER SYMBOL RATING UNTE Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 1.5 * # of component W Short circuit current IOS 50 mA Notes: Operation at above absolute maximum rating can adversely affect device reliability DC operating conditions (Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) ) PARAMETER SYMBOL MIN MAX UNIT NOTE Supply Voltage VDD 2.3 2.7 V I/O Supply Voltage VDDQ 2.3 2.7 V I/O Reference Voltage VREF 0.49*VDDQ 0.51*VDDQ V 1 I/O Termination Voltage(system) VTT VREF – 0.04 VREF + 0.04 V 2 Input High Voltage VIH (DC) VREF + 0.15 VREF + 0.3 V Input Low Voltage VIL (DC) -0.3 VREF - 0.15 V Input Voltage Level, CK and /CK inputs VIN (DC) -0.3 VDDQ + 0.3 V Input Differential Voltage, CK and /CK inputs VID (DC) 0.3 VDDQ + 0.6 V Input leakage current I LI -2 2 uA 3 Output leakage current I OZ -5 5 uA Output High current (Normal strength driver) ; VOUT=VTT + 0.84V I OH -16.8 mA Output Low current (Normal strength driver) ; VOUT=VTT - 0.84V I OL 16.8 mA Output High current (Half strength driver) ; VOUT=VTT + 0.45V I OH -9 mA Notes : 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH. 2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. |
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