HANBit

HDD64M72D18RPW

URL : www.hbe.co.kr

9

HANBit Electronics Co.,Ltd.

REV 1.0 (August.2002)

Data out high impedence time from

CK-/CK

-0.8

+0.8

-0.75

+0.75

-0.75

+0.75

ns

2

CK to valid DQS-in

0.75

1.25

0.75

1.25

0.75

1.25

DQS-in setup time

0

0

0

ns

3

DQS-in hold time

0.25

0.25

0.25

DQS-in falling edge to CK rising-setup

time

0.2

0.2

0.2

DQS-in falling edge to CK rising hold

time

0.2

0.2

0.2

DQS-in high level width

0.35

0.35

0.35

DQS-in low level width

0.35

0.35

0.35

DQS-in cycle time

0.9

1.1

0.9

1.1

0.9

1.1

Address and Control Input setup time

1.1

0.9

0.9

ns

Address and Control Input hold time

1.1

0.9

0.9

ns

Mode register set cycle time

16

15

15

ns

DQ & DM setup time to DQS

0.6

0.5

0.5

ns

DQ & DM hold time to DQS

0.6

0.5

0.5

ns

DQ & DM input pulse width

2

1.75

1.75

ns

Power down exit time

10

10

10

ns

Exit self refresh to write command

116

95

ns

Exit self refresh to bank active

command

80

75

75

ns

Exit self refresh to read command

200

200

200

Cycle

Refresh interval time

7.8

7.8

7.8

us

1

Output DQS valid window

0.35

0.35

0.35

DQS write postamble time

0.25

0.25

0.25

4

Notes :

1.

Maximum burst refresh of 8.

2.

referenced to a specific voltage level, but specify when the device output is no longer driving.

3.

The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going

from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was

4.

The maximum limit for this parameter is not a device limit. The device will operate with a great value for this

parameter, but system performance (bus turnaround) will degrade accordingly.