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HDD32M72B9-13B Datasheet(PDF) 4 Page - Hanbit Electronics Co.,Ltd |
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HDD32M72B9-13B Datasheet(HTML) 4 Page - Hanbit Electronics Co.,Ltd |
4 / 12 page HANBit HDD32M72B9 URL : www.hbe.co.kr 4 HANBit Electronics Co.,Ltd. REV 1.0 (July. 2003) PIN FUNCTION DESCRIPTION Pin Name Input Function CK, /CK Clock CK and CK are differential clock inputs. All address and control input signals are sam-pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE Clock Enable CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. /CS Chip Select CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 BA0 ~ BA1 Bank select address BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command is being applied. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. /WE Write enable Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. DQS0 ~ 8 Data Strobe Output with read data, input with write data. Edge -aligned with read data, cen- tered in write data. Used to capture write data. DM0~8 Input Data Mask DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. CB0 ~ 7 Check Bit Check Bits for ECC data are multiplexed on the same pins. VDDQ Supply DQ Power Supply : +2.5V ± 0.2V. VDD Supply Power Supply : +2.5V ± 0.2V (device specific). VSS Supply DQ Ground. VREF Supply SSTL_2 reference voltage. VDDSPD Supply Serial EEPROM Power Supply : 3.3v VDDID VDD identification Flag |
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