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HDD16M64D8W Datasheet(PDF) 6 Page - Hanbit Electronics Co.,Ltd

Part # HDD16M64D8W
Description  DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., DIMM,
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Manufacturer  HANBIT [Hanbit Electronics Co.,Ltd]
Direct Link  http://www.hbe.co.kr
Logo HANBIT - Hanbit Electronics Co.,Ltd

HDD16M64D8W Datasheet(HTML) 6 Page - Hanbit Electronics Co.,Ltd

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HANBit
HDD16M64D8W
URL : www.hbe.co.kr
6
HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)
INPUT/OUTPUT CAPACITANCE
(VDD = 2.5V, VDDQ = 2.5V, TA = 25°C, f = 1MHz)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE )
CIN1
49
57
pF
Input Capacitance(CKE0)
CIN2
42
50
pF
Input Capacitance( CS0)
CIN3
42
50
pF
Input Capacitance( CLK0, CLK1,CLK2 )
CIN4
22
25
pF
Data & DQS input/output Capacitance(DQ0~DQ63)
COUT1
6
8
pF
Input Capacitance(DM0~DM8)
CIN5
6
8
pF
AC TIMMING PARAMETERS & SPECIFICATIONS (THESEACCHARICTERISTICSWERETESTEDONTHECOMPONENT)
DDR200
DDR266A
DDR266B
-10A
-13A
-13B
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
NOTE
Row cycle time
tRC
70
65
65
ns
1
Refresh row cycle time
tRFC
80
75
75
ns
1,2
Row active time
tRAS
48
120K
45
120K
45
120K
ns
1,2
/RAS to /CAS delay
tRCD
20
20
20
ns
3
Row precharge time
tRP
20
20
20
ns
3
Row active to Row active delay
tRRD
15
15
15
ns
3
Write recovery time
tWR
2
2
2
tCK
3
Last data in to Read command
tCDLR
1
1
1
tCK
2
Col. address to Col. address delay
tCCD
1
1
1
tCK
CL=2.0
10
12
7.5
12
10
12
ns
Clock cycle time
CL=2.5
tCK
12
7.5
12
7.5
12
ns


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