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MC9S12XDP512 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MC9S12XDP512 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 28 page Features MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 3 • Programmable, high performance I/O co-processor module — up to 80 MIPS RISC performance • Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states • Performs logical, shifts, arithmetic, and bit operations on data • Enables FullCAN capability when used in conjunction with MSCAN module • Full LIN master or slave capability when used in conjunction with the six integrated LIN SCI modules • Can interrupt the HCS12X CPU signalling transfer completion • Triggers from any hardware module as well as from the CPU possible • 64K, 128K, 256K, 384K and 512K byte Flash • 128K and 256K ROM • Flash General Features – Erase sector size 1024 bytes – Automated program and erase algorithm – Fast sector erase and word program operation – 2-stage command pipeline for faster multi-word program times – Sector erase abort feature for critical interrupt response – Protection scheme to prevent accidental program or erase – Security option to prevent unauthorized access – Code integrity check using built-in data compression – Sense-amp margin level setting for reads • 1K, 2K, 4K byte EEPROM – Small erase sector (4 bytes) – Automated program and erase algorithm – Fast sector erase and word program operation – 2-stage command pipeline for faster multi-word program times – Sector erase abort feature for critical interrupt response – Protection scheme to prevent accidental program or erase • 4K, 8K, 12K, 14K, 16K, 20K, 32K Byte RAM |
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