Detailed Description

Programmable Registers

The MAX3570/MAX3571/MAX3573 include nine pro-

grammable registers (registers 1–9) consisting of six

divider registers (registers 1–6), one VCO control register

(register 7), and one test register (register 8). The final

register (register 9) controls the HI-IF filter frequency off-

set, as well as the DIV/LD output MUX status. Most regis-

ters contain some don’t care (X) bits. These can be

either a “0” or a “1” and do not affect the mode of opera-

tion (Table 1). Data is shifted in MSB first. Positive logic

is used.

3-Wire Serial Interface

The MAX3570 uses a 3-wire SPI/QSPI/MICROWIRE-

compatible serial interface. An active-low chip select

(CS) enables the device to receive data from the serial

input (SDA). Register address and data information are

clocked in on the rising edge of the serial clock signal

(SCL). While shifting in the serial data, the device

remains in its original configuration. A rising edge on

CS latches the data into the MAX3570’s internal regis-

ter, initiating the device’s change of state. Figure 1

shows the details of the 3-wire interface address and

data configuration.

2-Wire Serial Interface

serial interface. The serial bus is monitored continuous-

ly, waiting for a START condition followed by its

address. The address has 5 MSB internally set, while

the next two bits are set with external pins, ADDR2 and

ADDR1. The LSB determines whether it is a read or

write. When the device recognizes its address, it

acknowledges by pulling the SDA line low for one clock

period; it is then ready to accept the register address

for the first byte of data. Another acknowledge (ACK) is

sent once the register address is received. The device

is then ready to accept the data byte. More data bytes

can be sent for sequential registers, and ACK is sent

after each byte. After the final ACK is sent, the master

issues a STOP condition to free the bus. Figure 2 shows

the details of the 2-wire interface structure.

There is only one read-back register in the

MAX3571/MAX3573. To access it, send a START condi-

tion, and then the read address is set by the external

ADDR2 and ADDR1 pins. An ACK is sent, and the mas-

ter then begins to read from the slave. After the eight

bits have been read, the master should issue a no-

acknowledge (NACK), and then a STOP condition.

HI-IF Single-Chip Broadband Tuners

10

______________________________________________________________________________________

MSB

LSB

4 ADDRESS BITS

8 DATA BITS

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

Figure 1. 3-Wire Serial Interface Address and Data Configuration

DEVICE ADDRESS

REGISTER ADDRESS

DATA

DATA

START

8b11000<ADDR2><ADDR1>0

ACK

8b0000XXXX

ACK

D7–D0

ACK

D7–D0

ACK

STOP

Figure 2. 2-Wire Serial Interface Register Write Example

DEVICE ADDRESS

READ BYTE (8 Bits)

START

8b11000<ADDR2><ADDR1>1

ACK

8bXXXXXXXX

NACK

STOP

Figure 3. 2-Wire Serial Interface Register Read Example

ADDRESS (WRITE/READ)

ADDR2

ADDR1

Low

Low

Low

High

High

Low

High

High

Table 1. 2-Wire Serial Interface Address

Configuration (Set by ADDR2 and

ADDR1)

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