10

M65608E

4151I–AERO–03/04

Write Cycle 3 CS1 or CS2,

Controlled

Note:

The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and W LOW. Both signals must be

actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should

be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE =

V