K4X51163PC - L(F)E/G

February 2006

Mobile-DDR SDRAM

DC CHARACTERISTICS

°C)

Parameter

Symbol

Test Condition

DDR266

DDR222

Unit

Operating Current

(One Bank Active)

IDD0

tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH between valid commands;

address inputs are SWITCHING; data bus inputs are STABLE

80

70

mA

Precharge Standby Current in

power-down mode

IDD2P

all banks idle, CKE is LOW; CS is HIGH, tCK = t CKmin ; address and control inputs are

SWITCHING; data bus inputs are STABLE

0.3

mA

IDD2PS

all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control

inputs are SWITCHING; data bus inputs are STABLE

0.3

Precharge Standby Current

in non power-down mode

IDD2N

all banks idle, CKE is HIGH; CS is HIGH, tCK = t CKmin ;address and control inputs are

SWITCHING; data bus inputs are STABLE

12

10

mA

IDD2NS

all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control

inputs are SWITCHING; data bus inputs are STABLE

8

7

Active Standby Current

in power-down mode

IDD3P

one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin ;address and control inputs are

SWITCHING; data bus inputs are STABLE

6

mA

IDD3PS

one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;address and control

inputs are SWITCHING; data bus inputs are STABLE

3

Active Standby Current

in non power-down mode

(One Bank Active)

IDD3N

one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin ;address and control inputs

are SWITCHING; data bus inputs are STABLE

25

20

mA

IDD3NS

one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;

address and control inputs are SWITCHING; data bus inputs are STABLE

20

15

Operating Current

(Burst Mode)

IDD4R

one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts; I OUT = 0 mA

address inputs are SWITCHING; 50% data change each burst transfer

115

95

mA

IDD4W

one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;address inputs are

SWITCHING; 50% data change each burst transfer

100

90

Refresh Current

IDD5

tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;address and control inputs

are SWITCHING; data bus inputs are STABLE

150

135

mA

Self Refresh Current

IDD6

CKE is LOW; tCK = tCKmin ;

Extended Mode Register set to all 0’s;

address and control inputs are STABLE; data bus inputs

are STABLE

TCSR

85

°C

-E

Full Array

300

600

uA

1/2 Array

270

500

1/4 Array

255

450

-G

Full Array

250

500

1/2 Array

220

400

1/4 Array

205

350

Deep Power Down Current

Address and control inputs are STABLE; data bus inputs are STABLE

10

uA

Note :

2. DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.

Please contact Samsung for more information.

3. IDD specifications are tested after the device is properly intialized.

4. Input slew rate is 1V/ns.

STABLE is defined as inputs stable at a HIGH or LOW level ;

SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;

- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.