IC42S16101-5BG datasheet(7/78 Pages) ICSI

Part #	IC42S16101-5BG

Description	512K x 16 Bit x 2 Banks (16-MBIT) SDRAM

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Manufacturer	ICSI [Integrated Circuit Solution Inc]

Direct Link	http://www.icsi.com.tw

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IC42S16101

Integrated Circuit Solution Inc.

7

DR025-0F 01/17/2005

Notes:

1. When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated

voltages. Also note that the power-on sequence must be executed before starting memory operation.

2. Measured with tT = 1 ns.

3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and

VIL (max.).

4. Access time is measured at 1.4V with the load shown in the figure below.

5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL

(max.) when the output is in the high impedance state.

AC CHARACTERISTICS(1,2,3)

-5

-6

-7

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max Units

tCK3

Clock Cycle Time

CAS Latency = 3

5

—

6

—

7

—

ns

tCK2

CAS Latency = 2

7

—

8

—

8.6

—

ns

tAC3

Access Time From CLK(4)

CAS Latency = 3

—

4.5

—

5.5

—

6

ns

tAC2

CAS Latency = 2

—

5

—

6

—

6

ns

tCHI

CLK HIGH Level Width

2

—

2

—

2.5

—

ns

tCL

CLK LOW Level Width

2

—

2

—

2.5

—

ns

tOH

Output Data Hold Time

2

—

2

—

2

—

ns

tLZ

Output LOW Impedance Time

0

—

0

—

0

—

ns

tHZ3

Output HIGH Impedance Time(5)

CAS Latency = 3

—

4.5

—

5.5

—

6

ns

tHZ2

CAS Latency = 2

—

5

—

6

—

6

ns

tDS

Input Data Setup Time

2

—

2

—

2

—

ns

tDH

Input Data Hold Time

1

—

1

—

1

—

ns

tAS

Address Setup Time

2

—

2

—

2

—

ns

tAH

Address Hold Time

1

—

1

—

1

—

ns

tCKS

CKE Setup Time

2

—

2

—

2

—

ns

tCKH

CKE Hold Time

1

—

1

—

1

—

ns

tCKA

CKE to CLK Recovery Delay Time

1CLK+3 —

ns

tCS

Command Setup Time (CS, RAS, CAS, WE, DQM)

2

—

2

—

2

—

ns

tCH

Command Hold Time (CS, RAS, CAS, WE, DQM)

1

—

1

—

1

—

ns

tRC

Command Period (REF to REF / ACT to ACT)

50

—

60

—

70

—

ns

tRAS

Command Period (ACT to PRE)

30 100,000

36 100,000

42 100,000 ns

tRP

Command Period (PRE to ACT)

15

—

18

—

21

—

ns

tRCD

Active Command To Read / Write Command Delay Time

15

—

18

—

21

—

ns

tRRD

Command Period (ACT [0] to ACT[1])

10

—

12

—

14

—

ns

tDPL

Input Data To Precharge

2CLK

—

2CLK

—

2CLK

—

ns

Command Delay time

tDAL

Input Data To Active / Refresh

2CLK+tRP —

2CLK+tRP —ns

Command Delay time (During Auto-Precharge)

tTTransition Time

1

10

1

10

1

10

ns

tREF

Refresh Cycle Time (4096)

—

64

—

64

—

64

ms

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