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ICS8745B Datasheet(PDF) 10 Page - Integrated Circuit Systems |
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ICS8745B Datasheet(HTML) 10 Page - Integrated Circuit Systems |
10 / 15 page 8745BY www.icst.com/products/hiperclocks.html REV. B DECEMBER 2, 2004 10 Integrated Circuit Systems, Inc. ICS8745B 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR FIGURE 5A. ICS8745B LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE LAYOUT GUIDELINE The schematic of the ICS8745B layout example is shown in Figure 5A. The ICS8745B recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual sys- U3 8745 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR nQ1 Q1 GND nQ2 Q2 VDDO nQ3 Q3 SP = Space (i.e. not intstalled) C16 10u CLK_SEL C2 0.1uF VDDO=3.3V C11 0.01u RD3 SP VDD (U1-9) VDD=3.3V SEL[3:0] = 0101, Divide by 2 RU3 1K Zo = 50 Ohm (77.76 MHz) RU4 1K RU5 SP SEL0 RD4 SP (155.5 MHz) SEL2 RU6 1K C4 0.1uF C1 0.1uF RU7 SP 3.3V PECL Driver CLK_SEL RD2 1K RD5 1K VDDO SEL1 VDDO (U1-28) R8A 50 R7 10 R9 50 Zo = 50 Ohm R2 100 Decoupling capacitor located near the power pins R10 50 SEL3 RU2 SP RD6 SP R4 100 VDD SEL0 (U1-32) SEL2 C6 0.1uF RD7 1K Zo = 50 Ohm SEL1 3.3V (U1-16) PLL_SEL VDD VDD VDDA (U1-22) C5 0.1uF Zo = 50 Ohm LVDS_input + - tem will depend on the selected component types, the den- sity of the components, the density of the traces, and the stack up of the P.C. board. |
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