This Data Sheet may be revised by subsequent versions

©2003 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

10

EN29LV010

Rev. B, Issue Date: 2004/01/05

The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or

while in the autoselect mode. See next section for details on Reset.

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manufacturer and devices

codes, and determine whether or not a sector is protected. The Command Definitions table shows the

and is intended for PROM programmers.

Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.

Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of

times, without needing another command sequence.

The system must write the reset command to exit the autoselect mode and return to reading array data.

Programming Command

Programming the EN29LV010 is performed by using a four bus-cycle operation (two unlock write

cycles followed by the Program Setup command and Program Data Write cycle). When the program

command is executed, no additional CPU controls or timings are necessary. An internal timer

terminates the program operation automatically. Address is latched on the falling edge of CE or

bit). ). When the program operation is successfully completed, the device returns to read mode and

the user can read the data programmed to the device at that address. Note that data can not be

programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When

programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can

return the device to Read mode.

Unlock Bypass

To speed up programming operation, the Unlock Bypass Command may be used. Once this feature

is activated, the shorter two cycle Unlock Bypass Program command can be used instead of the

normal four cycle Program Command to program the device. This mode is exited after issuing the

Unlock Bypass Reset Command. The device powers up with this feature disabled.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the

chip erase command, which in turn invokes the Embedded Erase algorithm. The device does

the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and

verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required

to provide any controls or timings during these operations. The Command Definitions table shows the

address and data requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,

the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in

“AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing

waveforms.