© Semiconductor Components Industries, LLC, 2004

July, 2004 − Rev. 4

1

Publication Order Number:

DTA114EET1/D

DTA114EET1 Series

Preferred Devices

Bias Resistor Transistors

PNP Silicon Surface Mount Transistors

with Monolithic Bias Resistor Network

This new series of digital transistors is designed to replace a single

device and its external resistor bias network. The Bias Resistor

Transistor (BRT) contains a single transistor with a monolithic bias

network consisting of two resistors; a series base resistor and a

base−emitter resistor. The BRT eliminates these individual

components by integrating them into a single device. The use of a BRT

can reduce both system cost and board space. The device is housed in

the SC−75/SOT−416 package which is designed for low power

surface mount applications.

Features

The modified gull−winged leads absorb thermal stress during

soldering eliminating the possibility of damage to the die.

Rating

Symbol

Value

Unit

Collector-Base Voltage

50

Vdc

Collector-Emitter Voltage

50

Vdc

Collector Current

100

mAdc

Maximum ratings are those values beyond which device damage can occur.

Maximum ratings applied to the device are individual stress limit values (not

normal operating conditions) and are not valid simultaneously. If these limits

are exceeded, device functional operation is not implied, damage may occur

and reliability may be affected.

THERMAL CHARACTERISTICS

Rating

Symbol

Value

Unit

Total Device Dissipation, FR−4 Board

Derate above 25

°C

200

1.6

mW

mW/

°C

Thermal Resistance, Junction−to−Ambient

(Note 1)

600

°C/W

Total Device Dissipation, FR−4 Board

Derate above 25

°C

300

2.4

mW

mW/

°C

Thermal Resistance, Junction−to−Ambient

(Note 2)

400

°C/W

Junction and Storage Temperature Range

−55 to

+150

°C

1. FR−4 @ Minimum Pad.

2. FR−4 @ 1.0

× 1.0 Inch Pad.

SC−75/SOT−416

CASE 463

STYLE 1

Preferred devices are recommended choices for future use

and best overall value.

PNP SILICON BIAS

RESISTOR TRANSISTORS

3

2

1

PIN 3

COLLECTOR

(OUTPUT)

PIN 2

EMITTER

(GROUND)

PIN 1

BASE

(INPUT)

R1

R2

x

= Specific Device Code

M

= Date Code

MARKING

DIAGRAM

x M

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

*For additional information on our Pb−Free strategy

and soldering details, please download the

ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.