DS1845

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RANDOM READ

A random read requires a dummy byte write sequence to load in the data word address. Once the device

and data address bytes are clocked in by the master, and acknowledged by the DS1845, the master must

generate another start condition. The master now initiates a current address read by sending the device

address with the read/write bit set high. The DS1845 will acknowledge the device address and serially

clocks out the data byte.

SEQUENTIAL ADDRESS READ

Sequential reads are initiated by either a current address read or a random address read. After the master

receives the first data byte, the master responds with an acknowledge. As long as the DS1845 receives

this acknowledge after a byte is read, the master may clock out additional data words from the DS1845.

After reaching address FFh, it resets to address 00h.

The sequential read operation is terminated when the master initiates a stop condition. The master does

not respond with a zero.

For a more detailed description of 2-wire theory of operation, refer to the following section.

2-WIRE SERIAL PORT OPERATION

The 2-wire serial port interface supports a bi-directional data transmission protocol with device

addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as

a receiver. The device that controls the message is called a “master.” The devices that are controlled by

the master are “slaves.” The bus must be controlled by a master device that generates the serial clock

(SCL), controls the bus access, and generates the START and STOP conditions. The DS1845 operates as

a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.

The following I/O terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2. Timing diagrams for

the 2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is

provided in the AC Electrical Characteristics table for 2-wire serial communications.

The following bus protocol has been defined:

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Data transfer may be initiated only when the bus is not busy.

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During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is HIGH will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH

defines a START condition.

Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is

HIGH defines the STOP condition.