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DM74LS952 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DM74LS952 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 8 page TLF6437 August 1991 DM74LS952 (DM86LS52) Dual Rank 8-Bit TRI-STATE Shift Register General Description These circuits are TRI-STATE edge-triggered 8-bit IO reg- isters in parallel with 8-bit serial shift registers which are capable of operating in any of the following modes parallel load from IO pins to register ‘‘A’’ parallel transfer down from register ‘‘A’’ to serial shift register ‘‘B’’ parallel transfer up from shift register ‘‘B’’ to register ‘‘A’’ serial shift of regis- ter ‘‘B’’ synchronously clear Since the registers are edge- triggered by the positive transition of the clock the control lines which determine the mode or operation are completely independent of the logic level applied to the clock De- signed for bus-oriented systems these circuits have their TRI-STATE inputs and outputs on the same pins Features Y Registers are edge-triggered by the positive transition of the clock Y All inputs are PNP transistors Y Input disable dominates over output disable Y Output high impedance state does not impede any oth- er mode of operation Y 8-bit IO pins are TRI-STATE buffers Y Typical shift frequency is 36 MHz Y Typical power dissipation is 305 mW Y All control inputs are active when in an ‘‘L’’ logic state Y Devices can be cascaded into N-bit word Connection Diagram Dual-In-Line Package TLF6437 – 1 Top View Order Number DM74LS952N or DM86LS52N See NS Package Number N18A Pin Description DISO Output disable IS Serial input DISI Input disable DISTU Transfer up disable DISTD Transfer down disable DISS Shift disable OS Serial output CLKClock GNDGround IO 1 IO 88-bit IO pins VCC Supply Voltage TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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