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M61545AFP Datasheet(PDF) 5 Page - Renesas Technology Corp |
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M61545AFP Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 12 page M61545AFP Preliminary Rev.2.0 Dec 21, 2005 page 5 of 11 Relationship Between Data, Clock D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 DATA signal is read at rising edge of CLOCK. Latch signal is read at falling edge of CLOCK. Latch signal is “H”. Data Format for “H” & “L” DATA = “L” DATA =”H” DATA CLOCK For initialization, 2 blocks of identical 18-bit data need to be sent. The 2 blocks of data would set the operation condition for M61545AFP. This shown in figure below, DATA CLOCK 1 Block of Data st 2 Block of Data nd time 0.2sec There should be a delay of 0.2 second before the first block of Clock and Data appear. The interval between the 1st Block of data and the 2nd Block should be 0.2 second as well. This sequence is to ensure proper operation of M61545AFP due to the wide dynamic voltage range, which M61545AFP is made to cater for. This format of initialization needs to be done once only during every powering up of M61545AFP. It recommends to use external mute switch together because it might generate the shock noise during this initial setup timing. |
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