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ICS9248YF-195LF-T Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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ICS9248YF-195LF-T Datasheet(HTML) 4 Page - Integrated Circuit Systems |
4 / 16 page 4 ICS9248-195 0375D—02/02/04 Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to be floating (pulled up via internal resistor) at power-up. Byte 2: Active/Inactive Register (1 = enable, 0 = disable) t i B# n i PD W Pn o i t p i r c s e D 7 t i B7 1 ) s i D / n E ( F _ K L C I C P 6 t i B8 11 ) s i D / n E ( 6 K L C I C P 5 t i B7 11 ) s i D / n E ( 5 K L C I C P 4 t i B3 11 ) s i D / n E ( 4 K L C I C P 3 t i B2 11 ) s i D / n E ( 3 K L C I C P 2 t i B1 11 ) s i D / n E ( 2 K L C I C P 1 t i B0 11 ) s i D / n E ( 1 K L C I C P 0 t i B8 1 ) s i D / n E ( 0 K L C I C P Byte 1: Active/Inactive Register (1 = enable, 0 = disable) Byte 3: Active/Inactive Register (1 = enable, 0 = disable) t i B# n i PD W Pn o i t p i r c s e D 7 t i B- 1 ) d e v r e s e R ( 6 t i B6 41 ) s i D / n E ( F _ K L C U P C 5 t i B- 0 ) d e v r e s e R ( 4 t i B- 0 ) d e v r e s e R ( 3 t i B9 31 ) s i D / n E ( F _ M A R D S 2 t i B2 41 ) s i D / n E ( 2 K L C U P C 1 t i B3 41 ) s i D / n E ( 1 K L C U P C 0 t i B5 41 ) s i D / n E ( 0 K L C U P C t i B# n i PD W Pn o i t p i r c s e D 7 t i B- 1 ) d e v r e s e R ( 6 t i B- 0 ) d e v r e s e R ( 5 t i B- 0 ) d e v r e s e R ( 4 t i B- 0 ) d e v r e s e R ( 3 t i B8 21 ) s i D / n E ( 7 M A R D S 2 t i B9 21 ) s i D / n E ( 6 M A R D S 1 t i B1 31 ) s i D / n E ( 5 M A R D S 0 t i B2 31 ) s i D / n E ( 4 M A R D S |
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