 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ICS874003AGT Datasheet(PDF) 1 Page - Integrated Circuit Systems |
|
||||||||||||||||||||||||||||||
ICS874003AGT Datasheet(HTML) 1 Page - Integrated Circuit Systems |
|
|
1 / 12 page  Integrated Circuit Systems, Inc. 874003AG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006 1 ICS874003 PCI EXPRESS JITTER ATTENUATOR F_SELA 0 ÷5 (default) 1 ÷4 F_SELB 0 ÷5 (default) 1 ÷4 VCO 490 - 640MHz Phase Detector M = ÷5 (fixed) GENERAL DESCRIPTION The ICS874003 is a high performance Dif- ferential-to-LVDS Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003 has 3 PLL bandwidth modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 800kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have than x25 multipliers, the ICS874003 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the FSEL pins. The ICS874003 uses ICS 3rd Generation FemtoClockTM PLL technology to achive the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. FEATURES • Three Differential LVDS output pairs • One Differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 160MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 35ps (maximum) • 3.3V operating supply • Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages HiPerClockS™ ICS QA0 nQA0 BLOCK DIAGRAM BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~400kHz (default) 1 = PLL Bandwidth: ~800kHz PLL BANDWIDTH Pulldown OEA F_SELA BW_SEL CLK nCLK F_SELB MR OEB QA1 nQA1 QB0 nQB0 Pulldown Pulldown Pullup Pullup Pullup Float PIN ASSIGNMENT ICS874003 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View QA1 VDDO QA0 nQA0 MR BW_SEL nc VDDA F_SELA VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 VDDO QB1 nQB1 F_SELB OEB GND nCLK CLK OEA Pulldown 0 = ~200kHz Float = ~400kHz 1 = ~800kHz |
Similar Part No. - ICS874003AGT |
|
Similar Description - ICS874003AGT |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
