IS61LV3216

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. A

04/17/01

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

FEATURES

• High-speed access time: 10, 12, 15, and 20 ns

• CMOS low power operation

— 150 mW (typical) operating

— 150 µW (typical) standby

• TTL compatible interface levels

• Single 3.3V ± 10% power supply

• Fully static operation: no clock or refresh

required

• Three state outputs

• Industrial temperature available

• Available in 44-pin 400-mil SOJ package and

44-pin TSOP (Type 2)

32K x 16 LOW VOLTAGE CMOS STATIC RAM

DESCRIPTION

The

organized as 32,768 words by 16 bits. It is fabricated using

able process coupled with innovative circuit design tech-

niques, yields fast access times with low power consumption.

When

CE is HIGH (deselected), the device assumes a standby

mode at which the power dissipation can be reduced down

with CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs,

CE and OE. The active LOW Write

Enable (

WE) controls both writing and reading of the memory.A

data byte allows Upper Byte (

UB) and Lower Byte (LB) access.

The IS61LV3216 is packaged in the JEDEC standard 44-pin

400-mil SOJ and 44-pin TSOP (Type 2).

FUNCTIONAL BLOCK DIAGRAM

NOVEMBER 1997

A0-A14

CE

OE

WE

32K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB