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G924-285T1UF Datasheet(PDF) 6 Page - Global Mixed-mode Technology Inc

Part # G924-285T1UF
Description  300mA Low-Noise LDO Regulators
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Manufacturer  GMT [Global Mixed-mode Technology Inc]
Direct Link  http://www.gmt.com.tw
Logo GMT - Global Mixed-mode Technology Inc

G924-285T1UF Datasheet(HTML) 6 Page - Global Mixed-mode Technology Inc

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Ver: 0.2 Preliminary
Oct 01, 2004
TEL: 886-3-5788833
http://www.gmt.com.tw
6
G924
Global Mixed-mode Technology Inc.
Pin Description
PIN
NAME
FUNCTION
1
SHDN
Active-High Enable Input. A logic low reduces the supply current to less than 1µA. Connect to IN for
normal operation.
2
GND
Ground. This pin also functions as a heat sink. Solder to large pads or the circuit board ground
plane to maximize thermal dissipation.
3
BYP
This is a reference bypass pin. It should connect external 10nF capacitor to GND to reduce output
noise. Bypass capacitor must be no less than 1nF. (CBYP≥ 1nF)
4
OUT
Regulator Output. Sources up to 300mA. Bypass with a 1µF capacitor to GND.
5
VIN
Regulator Input. Supply voltage can range from +2.5V to +5.5V. Bypass with 1µF to GND.
Detailed Description
The block diagram of the G924 is shown in Figure 1. It
consists of an error amplifier, 1.20V bandgap refer-
ence, PMOS output transistor, internal feedback
voltage divider, shutdown logic, over current protection
circuit, and over temperature protection circuit.
The internal feedback voltage divider’s central tap is
connected to the non-inverting input of the error ampli-
fier. The error amplifier compares non-inverting input
with the 1.20V bandgap reference. If the feedback
voltage is higher than 1.20V, the error amplifier’s out-
put becomes higher so that the PMOS output transis-
tor has a smaller gate-to-source voltage (VGS). This
reduces the current carrying capability of the PMOS
output transistor, as a result the output voltage de-
creases until the feedback voltage is equal to 1.20V.
Similarly, when the feedback voltage is less than
1.20V, the error amplifier causes the output PMOS to
conduct more current to pull the feedback voltage up
to 1.20V. Thus, through this feedback action, the error
amplifier, output PMOS, and the voltage dividers effec-
tively form a unity-gain amplifier with the feedback
voltage force to be the same as the 1.20V bandgap
reference. The output voltage, VOUT, is then given by
the following equation:
VOUT = 1.20 (1 + R1/R2).
(1)
Alternatively, the relationship between R1 and R2 is
given by:
R1 = R2 (VOUT / 1.20 - 1).
(2)
For the output voltage versions of G924, the output
voltages are 1.20V for G924-120, 2.50V for G924-250,
3.30V for G924-330, etc.
Figure 1. Functional Diagram
SHDN
VIN
OUT
SHUTDOWN
LOGIC
1.2V
Vref
ERROR
AMP
OVER CURRENT
PROTECT & DYNAMIC
FEEDBACK
GND
R1
R2
OVER TEMP.
PROTECT
BYP
C
BYP
SHDN
VIN
OUT
SHUTDOWN
LOGIC
1.2V
Vref
ERROR
AMP
OVER CURRENT
PROTECT & DYNAMIC
FEEDBACK
GND
R1
R2
OVER TEMP.
PROTECT
BYP
C
BYP


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